Datasheet

PIC18CXX2
DS39026D-page 132  1999-2013 Microchip Technology Inc.
FIGURE 14-11: I
2
C SLAVE MODE WAVEFORM (RECEPTION 10-BIT ADDRESS)
SDA SCL SSPIF BF (SSPSTAT<0>)
S
1 234 56 789 1 2345 6789 1 2345 789
P
1 1 1 1 0 A9A8 A7 A6 A5 A4A3A2A1 A0 D7D6D5D4D3 D1D0
Receive Data Byte
ACK
R/W = 0
ACK
Receive First Byte of Address
Cleared in software
Bus Master
terminates transfer
D2
6
(PIR1<3>)
Receive Second Byte of Address
Cleared by hardware when SSPADD is updated with
UA (SSPSTAT<1>)
Clock is held low until update of SSPADD has taken place
UA is set indicating that the SSPADD needs to be updated
UA is set indicating that SSPADD needs to be updated
SSPBUF is written with contents of SSPSR
Dummy read of SSPBUF to clear BF flag
ACK
R/W = 1
Cleared in software
Dummy read of SSPBUF to clear BF flag
Read of SSPBUF clears BF flag
Cleared by hardware when SSPADD is updated with
low byte of address. high byte of address.