Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 117
PIC18CXX2
bit 3 S: START bit
(I
2
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.)
1 = Indicates that a START bit has been detected last (this bit is '0' on RESET)
0 = START bit was not detected last
bit 2 R/W
: Read/Write bit information (I
2
C mode only)
This bit holds the R/W bit information following the last address match. This bit is only valid from
the address match to the next START bit, STOP bit, or not ACK
bit.
In I
2
C Slave mode:
1 = Read
0 = Write
In
I
2
C Master mode:
1 = Transmit is in progress
0 = Transmit is not in progress
OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in
IDLE mode.
bit 1 UA: Update Address bit (10-bit I
2
C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0 BF: Buffer Full Status bit
Receive (SPI and
I
2
C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (
I
2
C mode only):
1 = Data transmit in progress (does not include the ACK
and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK
and STOP bits), SSPBUF is empty
REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER (CONTINUED)
R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0
SMP CKE D/A
PSR/WUA BF
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown