PIC18CXX2 High Performance Microcontrollers with 10-bit A/D Pin Diagrams DIP, Windowed CERDIP • C compiler optimized architecture/instruction set - Source code compatible with the PIC16CXX instruction set • Linear program memory addressing to 2 Mbytes • Linear data memory addressing to 4 Kbytes On-Chip Program Memory On-Chip RAM (bytes) Device EPROM (bytes) PIC18C242 16K 8192 512 PIC18C252 32K 16384 1536 PIC18C442 16K 8192 512 PIC18C452 32K 16384 1536 # Single Word Instructions • Up to
PIC18CXX2 RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 MCLR/VPP NC RB7 RB6 RB5 RB4 NC Pin Diagrams 6 5 4 3 2 1 44 43 42 41 40 PLCC 7 8 9 10 11 12 13 14 15 16 171 PIC18C4X2 28 27 26 25 24 23 22 21 20 19 8 RA4/T0CKI RA5/AN4/SS/LVDIN RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 VDD VSS OSC1/CLKI OSC2/CLKO/RA6 RC0/T1OSO/T1CKI NC 39 38 37 36 35 34 33 32 31 30 29 RB3/CCP2* RB2/INT2 RB1/INT1 RB0/INT0 VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0
PIC18CXX2 Pin Diagrams (Cont.
PIC18CXX2 Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 7 2.0 Oscillator Configurations........................................................................................................................................................... 17 3.0 Reset...............................................................................................
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PIC18CXX2 NOTES: DS39026D-page 6 1999-2013 Microchip Technology Inc.
PIC18CXX2 1.0 DEVICE OVERVIEW This document contains device specific information for the following four devices: 1. 2. 3. 4. The following two figures are device block diagrams sorted by pin count: 28-pin for Figure 1-1 and 40-pin for Figure 1-2. The 28-pin and 40-pin pinouts are listed in Table 1-2 and Table 1-3, respectively. PIC18C242 PIC18C252 PIC18C442 PIC18C452 These devices come in 28-pin and 40-pin packages.
PIC18CXX2 FIGURE 1-1: PIC18C2X2 BLOCK DIAGRAM Data Bus<8> 21 Table Pointer <2> 8 21 PORTA Data Latch 8 8 RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 Data RAM inc/dec logic 21 Address Latch 20 Address Latch Program Memory (up to 2M Bytes) PCLATU PCLATH PCU PCH PCL Program Counter Data Latch 12 Address<12> 12 4 BSR 31 Level Stack 16 (2) Decode Table Latch 4 Bank0, F FSR0 FSR1 FSR2 12 inc/dec logic 8 PORTB ROM Latch RB0/INT0 RB1/INT1 RB2/INT2 RB3/C
PIC18CXX2 FIGURE 1-2: PIC18C4X2 BLOCK DIAGRAM Data Bus<8> PORTA 21 8 21 Data RAM (up to 4K address reach) 8 8 inc/dec logic 21 Address Latch RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 Data Latch Table Pointer <2> Address Latch 20 Program Memory (up to 2M Bytes) (2) PCLATU PCLATH 12 Address<12> PCU PCH PCL Program Counter Data Latch 12 4 BSR FSR0 FSR1 FSR2 Bank0, F 31 Level Stack 16 PORTB 4 Decode Table Latch RB0/INT0 RB1/INT1 RB2/INT2 RB3/CCP2(1) RB7
PIC18CXX2 TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Name DIP MCLR/VPP MCLR 1 Pin SOIC Type Buffer Type 1 I ST P — — I ST I CMOS O — CLKO O — RA6 I/O TTL VPP NC OSC1/CLKI OSC1 — 9 — 9 CLKI OSC2/CLKO/RA6 OSC2 10 10 Description Master clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. These pins should be left unconnected. Oscillator crystal or external clock input.
PIC18CXX2 TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type SOIC Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/INT2 RB2 INT2 RB3/CCP2 RB3 CCP2 RB4 21 22 23 24 21 I/O I TTL ST Digital I/O. External Interrupt 0. I/O I TTL ST External Interrupt 1. I/O I TTL ST Digital I/O. External Interrupt 2.
PIC18CXX2 TABLE 1-2: PIC18C2X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type SOIC Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 RC0 I/O ST Digital I/O. T1OSO O — Timer1 oscillator output. T1CKI I ST Timer1/Timer3 external clock input. RC1/T1OSI/CCP2 12 12 RC1 I/O ST Digital I/O. T1OSI I CMOS Timer1 oscillator input. CCP2 I/O ST Capture2 input, Compare2 output, PWM2 output. RC2/CCP1 13 13 RC2 I/O ST Digital I/O.
PIC18CXX2 TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS Pin Number Pin Name DIP MCLR/VPP MCLR VPP NC OSC1/CLKI OSC1 1 Pin PLCC TQFP Type 2 18 I — 13 P — 14 30 I CLKI OSC2/CLKO/RA6 OSC2 I 14 15 31 O CLKO O RA6 I/O Buffer Type Description Master clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active low RESET to the device. Programming voltage input. — These pins should be left unconnected. Oscillator crystal or external clock input.
PIC18CXX2 TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type PLCC TQFP Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/INT2 RB2 INT2 RB3/CCP2 RB3 CCP2 RB4 RB5 RB6 33 34 35 36 36 37 38 39 8 I/O I TTL ST Digital I/O. External Interrupt 0. I/O I TTL ST External Interrupt 1. I/O I TTL ST Digital I/O. External Interrupt 2.
PIC18CXX2 TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type PLCC TQFP Buffer Type Description PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI RC1/T1OSI/CCP2 RC1 T1OSI CCP2 RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK 15 16 17 18 16 18 19 20 SCL 32 I/O O I ST — ST Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. I/O I I/O ST CMOS ST Digital I/O. Timer1 oscillator input.
PIC18CXX2 TABLE 1-3: PIC18C4X2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name DIP Pin Type PLCC TQFP RD0/PSP0 19 21 38 I/O RD1/PSP1 20 22 39 I/O RD2/PSP2 21 23 40 I/O RD3/PSP3 22 24 41 I/O RD4/PSP4 27 30 2 I/O RD5/PSP5 28 31 3 I/O RD6/PSP6 29 32 4 I/O RD7/PSP7 30 33 5 I/O RE0/RD/AN5 RE0 RD 8 9 25 I/O Buffer Type ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL ST TTL AN5 RE1/WR/AN6 RE1 WR 9 Analog AN6 RE2/CS/AN7 RE2 CS 10 10 26 Analo
PIC18CXX2 2.0 OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types TABLE 2-1: Ranges Tested: The PIC18CXX2 can be operated in eight different oscillator modes. The user can program three configuration bits (FOSC2, FOSC1, and FOSC0) to select one of these eight modes: 1. 2. 3. 4. LP XT HS HS + PLL 5. 6. RC RCIO 7. 8. EC ECIO 2.
PIC18CXX2 TABLE 2-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATORS FIGURE 2-2: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP CONFIGURATION) Ranges Tested: Mode Freq C1 C2 LP 32.0 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF XT HS OSC1 Clock from Ext. System PIC18CXXX OSC2 Open 200 kHz 47-68 pF 47-68 pF 1.0 MHz 15 pF 15 pF 4.0 MHz 15 pF 15 pF 2.3 4.0 MHz 15 pF 15 pF 8.0 MHz 15-33 pF 15-33 pF 20.0 MHz 15-33 pF 15-33 pF 25.
PIC18CXX2 2.4 FIGURE 2-5: External Clock Input The EC and ECIO oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. 2.5 HS/PLL The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode.
PIC18CXX2 2.6 Oscillator Switching Feature The PIC18CXX2 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18CXX2 devices, this alternate clock source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has FIGURE 2-7: been enabled, the device can switch to a low power execution mode.
PIC18CXX2 2.6.2 OSCILLATOR TRANSITIONS A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-8. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles.
PIC18CXX2 frequency. A timing diagram, indicating the transition from the Timer1 oscillator to the main oscillator for HS-PLL mode, is shown in Figure 2-10. If the main oscillator is configured for HS-PLL mode, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur.
PIC18CXX2 2.7 Effects of SLEEP Mode on the On-chip Oscillator When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor TABLE 2-3: switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents).
PIC18CXX2 NOTES: DS39026D-page 24 1999-2013 Microchip Technology Inc.
PIC18CXX2 3.0 RESET The PIC18CXX2 differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset A simplified block diagram of the On-Chip Reset Circuit is shown in Figure 3-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path.
PIC18CXX2 3.1 Power-on Reset (POR) A Power-on Reset pulse is generated on-chip when VDD rise is detected. To take advantage of the POR circuitry, just tie the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (i.e.
PIC18CXX2 TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) Oscillator Configuration PWRTE = 0 PWRTE = 1 72 ms + 1024TOSC 1024TOSC + 2ms + 2 ms HS, XT, LP 72 ms + 1024TOSC 1024TOSC EC 72 ms — External RC 72 ms — Note 1: 2 ms is the nominal time required for the 4x PLL to lock. 2: 72 ms is the nominal Power-up Timer delay.
PIC18CXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TOSU 242 442 252 452 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3) TOSL 242 442 252 452 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 242 442 252 452 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 242 442 252 452 ---0 0000 ---0 0000 ---u uuuu PCLATH 242 442 252 452 0000
PIC18CXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt FSR1H 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu FSR1L 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu BSR 242 442 252 452 ---- 0000 ---- 0000 ---- uuuu INDF2 242 442 252 452 N/A N/A N/A POSTINC2 242 442 252 452 N/A N/A N/A POSTDEC2 242 442 252 452 N/A N/A N/A PREINC2 242 442 252 452
PIC18CXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt ADRESH ADRESL ADCON0 ADCON1 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON TMR3H TMR3L T3CON SPBRG RCREG TXREG TXSTA RCSTA IPR2 PIR2 PIE2 IPR1 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu 242 442 252 452 0000 0000 0000 0000 uuuu uuuu 242 442
PIC18CXX2 TABLE 3-3: Register INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Resets WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISD TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu TRISA(5, 7) 242 442 252 452 -111 1111(5) -111 1111(5) -uuu uuuu(5) LATE 242 44
PIC18CXX2 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 3-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 3-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS39026D-page 32 1999-2013 Microchip Technology I
PIC18CXX2 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 1V 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 1999-2013 Microchip Technology Inc.
PIC18CXX2 NOTES: DS39026D-page 34 1999-2013 Microchip Technology Inc.
PIC18CXX2 4.0 MEMORY ORGANIZATION There are two memory blocks in Enhanced MCU devices. These memory blocks are: • Program Memory • Data Memory Program and data memory use separate buses so that concurrent access can occur. 4.1 Program Memory Organization A 21-bit program counter is capable of addressing the 2-Mbyte program memory space. Accessing a location between the physically implemented memory and the 2-Mbyte address will cause a read of all ’0’s (a NOP instruction).
PIC18CXX2 FIGURE 4-1: PROGRAM MEMORY MAP AND STACK FOR PIC18C442/242 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 FIGURE 4-2: PROGRAM MEMORY MAP AND STACK FOR PIC18C452/252 PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 Stack Level 31 RESET Vector RESET Vector 0000h 0000h High Priority Interrupt Vector 0008h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h Low Priority Interrupt Vector 0018h On-chip Program Memory On
PIC18CXX2 4.2 Return Address Stack The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the call or return instructions.
PIC18CXX2 REGISTER 4-1: STKPTR REGISTER R/C-0 STKFUL R/C-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 STKUNF — SP4 SP3 SP2 SP1 SP0 bit 7 bit 0 bit 7(1) STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed bit 6(1) STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur bit 5 Unimplemented: Read as '0' bit 4-0 SP4:SP0: Stack Pointer Location bits Note 1: Bit 7 and bit 6 can only be cleared in user s
PIC18CXX2 4.3 Fast Register Stack 4.4 A "fast interrupt return" option is available for interrupts. A Fast Register Stack is provided for the STATUS, WREG and BSR registers and are only one in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the registers are then loaded back into the working registers, if the FAST RETURN instruction is used to return from the interrupt.
PIC18CXX2 4.6 Instruction Flow/Pipelining A fetch cycle begins with the program counter (PC) incrementing in Q1. An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18CXX2 4.7.1 TWO-WORD INSTRUCTIONS The PIC18CXX2 devices have four two-word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSBs set to 1’s and is a special kind of NOP instruction. The lower 12bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed.
PIC18CXX2 4.9 Data Memory Organization The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-6 and Figure 4-7 show the data memory organization for the PIC18CXX2 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented.
PIC18CXX2 FIGURE 4-6: DATA MEMORY MAP FOR PIC18C242/442 BSR<3:0> = 0000b = 0001b Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 000h 07Fh 080h 0FFh 100h GPR Bank 1 1FFh FFh 200h Access Bank 00h 7Fh 80h Access RAM high FFh (SFR’s) Access RAM low = 0010b = 1110b = 1111b Bank 2 to Bank 14 Unused Read ’00h’ 00h Unused FFh SFR Bank 15 EFFh F00h F7Fh F80h FFFh When a = 0, the BSR is ignored and the Access Bank is used. The first 128 bytes are General Purpose RAM (from Bank 0).
PIC18CXX2 FIGURE 4-7: DATA MEMORY MAP FOR PIC18C252/452 BSR<3:0> = 0000b = 0001b Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 GPR Bank 1 FFh 00h = 0010b Bank 2 = 0011b 1FFh 200h GPR 2FFh 300h FFh 00h Bank 3 GPR 3FFh 400h FFh = 0100b = 0101b Bank 4 = 1110b = 1111b Access Bank GPR 4FFh 500h 00h GPR Bank 5 FFh = 0110b 000h 07Fh 080h 0FFh 100h Bank 6 to Bank 14 5FFh 600h Unused Read ’00h’ 00h Unused FFh SFR Bank 15 EFFh F00h F7Fh F80h FFFh 00h 7Fh 80h Access RAM high FFh
PIC18CXX2 TABLE 4-1: FFFh FFEh FFDh SPECIAL FUNCTION REGISTER MAP TOSU FDFh TOSH TOSL INDF2(3) FBFh CCPR1H F9Fh IPR1 FDEh POSTINC2 (3) FBEh CCPR1L F9Eh PIR1 FDDh POSTDEC2(3) FBDh CCP1CON F9Dh PIE1 (3) FFCh STKPTR FDCh PREINC2 FBCh CCPR2H F9Ch — FFBh PCLATU FDBh PLUSW2(3) FBBh CCPR2L F9Bh — FFAh PCLATH FDAh FSR2H FBAh CCP2CON F9Ah — FF9h PCL FD9h FSR2L FB9h — F99h — F98h — FF8h TBLPTRU FD8h STATUS FB8h — FF7h TBLPTRH FD7h TMR0H FB7h — F97h
PIC18CXX2 TABLE 4-2: File Name REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Details on page: ---0 0000 37 TOSH Top-of-Stack High Byte (TOS<15:8>) 0000 0000 37 TOSL Top-of-Stack Low Byte (TOS<7:0>) 0000 0000 37 TOSU STKPTR PCLATU Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR STKFUL STKUNF — Return Stack Pointer 00-0 0000 38 — — — Holding Register for PC<20:16> ---0 0000 39 PCLATH Holding Register for PC<15:8> 0000 0000 39 PCL
PIC18CXX2 TABLE 4-2: File Name WDTCON RCON REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — IPEN LWRT — RI TO Bit 2 Value on POR, BOR Details on page: Bit 1 Bit 0 — — SWDTE ---- ---0 183 PD POR BOR 0q-1 11qq 53, 56, 74 97 TMR1H Timer1 Register High Byte xxxx xxxx TMR1L Timer1 Register Low Byte xxxx xxxx 97 0-00 0000 97 T1CON RD16 — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON TMR2 Timer2 Register 0000 0000 101 PR2 Timer2 Period R
PIC18CXX2 TABLE 4-2: REGISTER FILE SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: IPR2 — — — — BCLIP LVDIP TMR3IP CCP2IP ---- 1111 73 PIR2 — — — — BCLIF LVDIF TMR3IF CCP2IF ---- 0000 69 PIE2 — — — — BCLIE LVDIE TMR3IE CCP2IE ---- 0000 71 IPR1 PSPIP ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 1111 1111 72 PIR1 PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 68 PIE1 PSPIE ADIE R
PIC18CXX2 4.10 Access Bank can be accessed without any software overhead. This is useful for testing status flags and modifying control bits. The Access Bank is an architectural enhancement, which is very useful for C compiler code optimization. The techniques used by the C compiler may also be useful for programs written in assembly. 4.11 The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks.
PIC18CXX2 4.12 Indirect Addressing, INDF and FSR Registers Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. An FSR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-9 shows the operation of indirect addressing.
PIC18CXX2 If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or postincrement/decrement functions.
PIC18CXX2 4.13 STATUS Register The STATUS register, shown in Register 4-2, contains the arithmetic status of the ALU. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic.
PIC18CXX2 4.13.1 RCON REGISTER . Note 1: If the BOREN configuration bit is set (Brown-out Reset enabled), the BOR bit is ’1’ on a Power-on Reset. After a Brownout Reset has occurred, the BOR bit will be clear and must be set by firmware to indicate the occurrence of the next Brownout Reset. If the BOREN configuration bit is clear (Brown-out Reset disabled), BOR is unknown after Power-on Reset and Brown-out Reset conditions.
PIC18CXX2 NOTES: DS39026D-page 54 1999-2013 Microchip Technology Inc.
PIC18CXX2 5.0 TABLE READS/TABLE WRITES Table Read operations retrieve data from program memory and place it into the data memory space. Figure 5-1 shows the operation of a Table Read with program and data memory. Enhanced devices have two memory spaces: the program memory space and the data memory space. The program memory space is 16-bits wide, while the data memory space is 8 bits wide.
PIC18CXX2 5.1 5.1.1 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include the: • TBLPTR registers • TABLAT register • RCON register REGISTER 5-1: RCON REGISTER The LWRT bit specifies the operation of Table Writes to internal memory when the VPP voltage is applied to the MCLR pin.
PIC18CXX2 5.1.2 TABLAT - TABLE LATCH REGISTER 5.1.3 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data memory. TBLPTR - TABLE POINTER REGISTER The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers (Table Pointer Upper Byte, High Byte and Low Byte).
PIC18CXX2 FIGURE 5-3: HOLDING REGISTER AND THE WRITE BLOCK Program Memory (x 2-bits) Block n Write Block MSB Holding Register Block n + 1 Block n + 2 The write to the MSB of the Write Block causes the entire block to be written to program memory. The program memory block that is written depends on the address that is written to in the MSB of the Write Block. 5.2.2.1 Operation The long write is what actually programs words of data into the internal memory.
PIC18CXX2 5.2.3 INTERRUPTS Depending on the states of interrupt priority bits, the GIE/GIEH bit or the PIE/GIEL bit, program execution can either be vectored to the high or low priority Interrupt Service Routine (ISR), or continue execution from where programming commenced. The long write must be terminated by a RESET or any interrupt. The interrupt source must have its interrupt enable bit set. When the source sets its interrupt flag, programming will terminate.
PIC18CXX2 NOTES: DS39026D-page 60 1999-2013 Microchip Technology Inc.
PIC18CXX2 6.0 8 X 8 HARDWARE MULTIPLIER Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: 6.1 Introduction • Higher computational throughput • Reduces code size requirements for multiply algorithms An 8 x 8 hardware multiplier is included in the ALU of the PIC18CXX2 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC18CXX2 EXAMPLE 6-3: MOVF MULWF 16 x 16 UNSIGNED MULTIPLY ROUTINE EXAMPLE 6-4: ARG1L, W ARG2L MOVFF MOVFF ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; MOVF MULWF ARG1H, W ARG2H ; MOVF MULWF 16 x 16 SIGNED MULTIPLY ROUTINE ARG1L, W ARG2L MOVFF MOVFF ; ARG1L * ARG2L -> ; PRODH:PRODL PRODH, RES1 ; PRODL, RES0 ; MOVF MULWF ARG1H, W ARG2H ; MOVFF MOVFF ; ARG1H * ARG2H -> ; PRODH:PRODL PRODH, RES3 ; PRODL, RES2 ; MOVF MULWF ARG1L, W ARG2H MOVF ADDWF MOVF ADDWFC CLRF ADDWFC
PIC18CXX2 7.0 INTERRUPTS The PIC18CXX2 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level, or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are ten registers which are used to control interrupt operation.
PIC18CXX2 FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Wake-up if in SLEEP mode Interrupt to CPU Vector to location 0008h GIEH/GIE TMR1IF TMR1IE TMR1IP IPE IPEN XXXXIF XXXXIE XXXXIP GIEL/PEIE IPEN Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation Peripheral Interrupt Flag bit
PIC18CXX2 7.1 INTCON Registers The INTCON Registers are readable and writable registers, which contains various enable, priority, and flag bits.
PIC18CXX2 REGISTER 7-2: INTCON2 REGISTER R/W-1 RBPU R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 U-0 R/W-1 U-0 R/W-1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0:External Interrupt0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge bit 5 INTEDG1: External Interrupt1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling
PIC18CXX2 REGISTER 7-3: INTCON3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5 Unimplemented: Read as '0' bit 4 INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt bit 3
PIC18CXX2 7.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Flag Registers (PIR1, PIR2). Note 1: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>).
PIC18CXX2 REGISTER 7-5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (PIR2) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — BCLIF LVDIF TMR3IF CCP2IF bit 7 bit 0 bit 7-4 Unimplemented: Read as '0' bit 3 BCLIF: Bus Collision Interrupt Flag bit 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred bit 2 LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the
PIC18CXX2 7.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable Registers (PIE1, PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18CXX2 REGISTER 7-7: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (PIE2) U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — BCLIE LVDIE TMR3IE CCP2IE bit 7 bit 0 bit 7-4 Unimplemented: Read as '0' bit 3 BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit 2 LVDIE: Low Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt bit 0 CCP2IE
PIC18CXX2 7.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority Registers (IPR1, IPR2). The operation of the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18CXX2 REGISTER 7-9: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (IPR2) U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — BCLIP LVDIP TMR3IP CCP2IP bit 7 bit 0 bit 7-4 Unimplemented: Read as '0' bit 3 BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority bit 2 LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: CCP2 Interrupt P
PIC18CXX2 7.5 RCON Register The RCON register contains the bit which is used to enable prioritized interrupts (IPEN).
PIC18CXX2 7.6 INT0 Interrupt 7.7 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge triggered: either rising, if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxE.
PIC18CXX2 NOTES: DS39026D-page 76 1999-2013 Microchip Technology Inc.
PIC18CXX2 8.0 I/O PORTS Depending on the device selected, there are either five ports, or three ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18CXX2 FIGURE 8-2: BLOCK DIAGRAM OF RA4/T0CKI PIN FIGURE 8-3: BLOCK DIAGRAM OF RA6 ECRA6 or RCRA6 Enable Data Bus RD LATA Data Bus WR LATA or PORTA WR TRISA RD LATA D Q CK Q D N Data Latch D Q CK Q I/O pin VDD WR LATA or PORTA TRIS Latch CK Q D WR TRISA CK N Q VSS Data Bus Q I/O pin(1) Q TRIS Latch RD TRISA P Data Latch VSS Schmitt Trigger Input Buffer Q (1) ECRA6 or RCRA6 Enable TTL Input Buffer D RD TRISA ENEN RD PORTA Data Bus Q TMR0 Clock Input Note 1: I/O pins h
PIC18CXX2 TABLE 8-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input. RA1/AN1 bit1 TTL Input/output or analog input. RA2/AN2/VREF- bit2 TTL Input/output or analog input or VREF-. RA3/AN3/VREF+ bit3 TTL Input/output or analog input or VREF+. RA4/T0CKI bit4 ST Input/output or external clock input for Timer0. Output is open drain type.
PIC18CXX2 8.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Note: On a Power-on Reset, these pins are configured as digital inputs.
PIC18CXX2 FIGURE 8-5: BLOCK DIAGRAM OF RB2:RB0 PINS VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D WR Port Q I/O pin(1) CK TRIS Latch D WR TRIS Q TTL Input Buffer CK RD TRIS Q D EN RD Port RB0/INT Schmitt Trigger Buffer RD Port Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
PIC18CXX2 TABLE 8-3: PORTB FUNCTIONS Name Bit# Buffer RB0/INT0 bit0 TTL/ST(1) Input/output pin or external interrupt input1. Internal software programmable weak pull-up. RB1/INT1 bit1 TTL/ST(1) Input/output pin or external interrupt input2. Internal software programmable weak pull-up. RB2/INT2 bit2 TTL/ST(1) Input/output pin or external interrupt input3. Internal software programmable weak pull-up. RB3/CCP2(3) bit3 TTL/ST(4) Input/output pin.
PIC18CXX2 8.3 PORTC, TRISC and LATC Registers The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. PORTC is an 8-bit wide, bi-directional port. The corresponding Data Direction Register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode).
PIC18CXX2 TABLE 8-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit1 ST Input/output port pin, Timer1 oscillator input, or Capture2 input/ Compare2 output/PWM output when CCP2MX configuration bit is disabled. RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output.
PIC18CXX2 8.4 PORTD, TRISD and LATD Registers FIGURE 8-8: PORTD BLOCK DIAGRAM IN I/O PORT MODE This section is only applicable to the PIC18C4X2 devices. PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e.
PIC18CXX2 TABLE 8-7: PORTD FUNCTIONS Name Bit# Buffer Type RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0. RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1. bit2 ST/TTL (1) Input/output port pin or parallel slave port bit2. bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3. RD4/PSP4 bit4 ST/TTL (1) Input/output port pin or parallel slave port bit4.
PIC18CXX2 8.5 PORTE, TRISE and LATE Registers FIGURE 8-9: PORTE BLOCK DIAGRAM IN I/O PORT MODE This section is only applicable to the PIC18C4X2 devices. PORTE is a 3-bit wide, bi-directional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e.
PIC18CXX2 REGISTER 8-1: TRISE REGISTER R-0 IBF R-0 OBF R/W-0 IBOV R/W-0 U-0 R/W-1 R/W-1 R/W-1 PSPMODE — TRISE2 TRISE1 TRISE0 bit 7 bit 0 bit 7 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received bit 6 OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5 IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write oc
PIC18CXX2 TABLE 8-9: PORTE FUNCTIONS Name Bit# RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 bit0 bit1 bit2 Buffer Type Function ST/TTL(1) Input/output port pin or read control input in Parallel Slave Port mode or analog input: RD 1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected). ST/TTL(1) Input/output port pin or write control input in Parallel Slave Port mode or analog input: WR 1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected).
PIC18CXX2 8.6 FIGURE 8-10: Parallel Slave Port PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) The Parallel Slave Port is implemented on the 40-pin devices only (PIC18C4X2). PORTD operates as an 8-bit wide, parallel slave port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. It is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR.
PIC18CXX2 FIGURE 8-12: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 8-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on POR, BOR Value on all other RESETS Port Data Latch when written; Port pins when read xxxx xxxx uuuu uuuu LATD LATD Data Output bits xxxx xxxx uuuu uuuu TRISD PORTD Data Direction bits 1111 1111 1111 1111 ---- -000 ---- -000 ---- -xxx ---- -uuu Name PORTD Bit 7 Bit 6 Bit 5 Bit 4 B
PIC18CXX2 NOTES: DS39026D-page 92 1999-2013 Microchip Technology Inc.
PIC18CXX2 9.0 TIMER0 MODULE Figure 9-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 9-2 shows a simplified block diagram of the Timer0 module in 16-bit mode.
PIC18CXX2 FIGURE 9-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 1 Programmable Prescaler RA4/T0CKI pin 1 Sync with Internal Clocks TMR0 (2 TCY delay) T0SE 3 PSA Set Interrupt Flag bit TMR0IF on Overflow T0PS2, T0PS1, T0PS0 T0CS Note: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale.
PIC18CXX2 9.1 Timer0 Operation 9.2.1 Timer0 can operate as a timer or as a counter. The prescaler assignment is fully under software control (i.e., it can be changed “on-the-fly” during program execution). Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0 register is written, the increment is inhibited for the following two instruction cycles.
PIC18CXX2 NOTES: DS39026D-page 96 1999-2013 Microchip Technology Inc.
PIC18CXX2 10.0 TIMER1 MODULE Figure 10-1 is a simplified block diagram of the Timer1 module. The Timer1 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR1H and TMR1L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module special event trigger REGISTER 10-1: Register 10-1 details the Timer1 control register.
PIC18CXX2 10.1 Timer1 Operation When TMR1CS = 0, Timer1 increments every instruction cycle. When TMR1CS = 1, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. Timer1 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.
PIC18CXX2 10.2 Timer1 Oscillator 10.4 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 10-1 shows the capacitor selection for the Timer1 oscillator.
PIC18CXX2 TABLE 10-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Value on all other RESETS INTCON GIE/GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP T
PIC18CXX2 11.0 TIMER2 MODULE 11.1 The Timer2 module timer has the following features: • • • • • • • 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 has a control register shown in Register 11-1.
PIC18CXX2 11.2 Timer2 Interrupt 11.3 The Timer2 module has an 8-bit period register, PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. FIGURE 11-1: Output of TMR2 The output of TMR2 (before the postscaler) is fed to the Synchronous Serial Port module, which optionally uses it to generate the shift clock.
PIC18CXX2 12.0 TIMER3 MODULE Figure 12-1 is a simplified block diagram of the Timer3 module. The Timer3 module timer/counter has the following features: • 16-bit timer/counter (two 8-bit registers: TMR3H and TMR3L) • Readable and writable (both registers) • Internal or external clock select • Interrupt-on-overflow from FFFFh to 0000h • Reset from CCP module trigger REGISTER 12-1: Register 12-1 shows the Timer3 control register.
PIC18CXX2 12.1 Timer3 Operation When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. Timer3 can operate in one of these modes: • As a timer • As a synchronous counter • As an asynchronous counter When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored.
PIC18CXX2 12.2 Timer1 Oscillator 12.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON<3>) bit. The oscillator is a low power oscillator rated up to 200 KHz. See Section 10.0 for further details. 12.3 If the CCP module is configured in Compare mode to generate a “special event trigger” (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3.
PIC18CXX2 NOTES: DS39026D-page 106 1999-2013 Microchip Technology Inc.
PIC18CXX2 13.0 CAPTURE/COMPARE/PWM (CCP) MODULES Each CCP (Capture/Compare/PWM) module contains a 16-bit register which can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM master/slave Duty Cycle register. Table 13-1 shows the timer resources of the CCP module modes. REGISTER 13-1: The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger.
PIC18CXX2 13.1 CCP1 Module 13.2 Capture/Compare/PWM Register 1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 13-1: Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable.
PIC18CXX2 13.3 13.3.3 Capture Mode In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1. An event is defined as: • • • • every falling edge every rising edge every 4th rising edge every 16th rising edge 13.3.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: 13.3.
PIC18CXX2 13.4 13.4.2 Compare Mode Timer1 and/or Timer3 must be running in Timer mode, or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value or the TMR3 register pair value. When a match occurs, the RC2/CCP1 (RC1/CCP2) pin is: • • • • TIMER1/TIMER3 MODE SELECTION 13.4.
PIC18CXX2 TABLE 13-3: Name REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Value on POR, BOR Value on all other RESETS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTCON GIE/GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000
PIC18CXX2 13.5 13.5.1 PWM Mode In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 13-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC18CXX2 13.5.3 SETUP FOR PWM OPERATION 3. The following steps should be taken when configuring the CCP module for PWM operation: 4. 1. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 2. TABLE 13-4: Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation.
PIC18CXX2 NOTES: DS39026D-page 114 1999-2013 Microchip Technology Inc.
PIC18CXX2 14.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE 14.1 Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18CXX2 14.2 Control Registers The MSSP module has three associated registers. These include a status register (SSPSTAT) and two control registers (SSPCON1 and SSPCON2).
PIC18CXX2 REGISTER 14-1: SSPSTAT: MSSP STATUS REGISTER (CONTINUED) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 3 S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
PIC18CXX2 REGISTER 14-2: SSPCON1: MSSP CONTROL REGISTER1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collis
PIC18CXX2 REGISTER 14-2: SSPCON1: MSSP CONTROL REGISTER1 (CONTINUED) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.
PIC18CXX2 REGISTER 14-3: SSPCON2: MSSP CONTROL REGISTER2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was
PIC18CXX2 14.3 SPI Mode FIGURE 14-1: The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported.
PIC18CXX2 When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a EXAMPLE 14-1: transmitter.
PIC18CXX2 14.3.3 TYPICAL CONNECTION Figure 14-2 shows a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCK signal. Data is shifted out of both shift registers on their programmed clock edge, and latched on the opposite edge of the clock. Both processors should be programmed to same Clock Polarity (CKP), then both con- FIGURE 14-2: trollers would send and receive data at the same time.
PIC18CXX2 14.3.4 MASTER MODE Figure 14-3, Figure 14-5, and Figure 14-6, where the MSB is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 14-2) is to broadcast data by the software protocol. • • • • In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to.
PIC18CXX2 14.3.5 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output.
PIC18CXX2 FIGURE 14-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit0 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF FIGURE 14-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS not optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit
PIC18CXX2 14.3.7 SLEEP OPERATION 14.3.9 In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 14-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 14-1: In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device.
PIC18CXX2 14.4 MSSP I2C Operation The MSSP module in I 2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/ SCK/SCL pin, which is the clock (SCL), and the RC4/ SDI/SDA pin, which is the data (SDA).
PIC18CXX2 14.4.1.1 Addressing Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC18CXX2 I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) FIGURE 14-8: Receiving Address Receiving Data R/W=0 Receiving Data Not ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SDA SCL 1 S 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 SSPIF P Bus Master terminates transfer BF (SSPSTAT<0>) Cleared in software SSPBUF register is read SSPOV (SSPCON1<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent.
1999-2013 Microchip Technology Inc. 2 UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 S SCL 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK Receive First Byte of Address R/W = 0 1 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated.
DS39026D-page 132 UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 2 1 3 1 5 0 6 A9 7 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 4 1 9 ACK R/W = 0 1 2 3 A5 4 A4 Cleared in software A6 5 A3 6 A2 7 A1 8 A0 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC18CXX2 14.4.2 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18CXX2 I2C MASTER MODE SUPPORT Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. Once Master mode is enabled, the user has six options. 1. 2. 3. 4. 5. 6. Assert a START condition on SDA and SCL. Assert a Repeated START condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Generate a STOP condition on SDA and SCL. Configure the I2C port to receive data.
PIC18CXX2 14.4.4.1 I2C Master Mode Operation A typical transmit sequence would go as follows: The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. a) In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18CXX2 14.4.5 BAUD RATE GENERATOR remented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. If Clock Arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 14-15). In I2C Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 14-14).
PIC18CXX2 14.4.6 I2C MASTER MODE START CONDITION TIMING 14.4.6.1 If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC18CXX2 14.4.7 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode).
PIC18CXX2 14.4.8 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the buffer full flag bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106).
DS39026D-page 140 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 cleared in software 2 6 7 8 9 After START condition SEN cleared by hardware.
1999-2013 Microchip Technology Inc.
PIC18CXX2 14.4.10 ACKNOWLEDGE SEQUENCE TIMING 14.4.11 A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the STOP sequence enable bit, PEN (SSPCON2<2>). At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0.
PIC18CXX2 FIGURE 14-21: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for Tbrg, followed by SDA = 1 for Tbrg after SDA sampled high. P bit (SSPSTAT<4>) is set Write to SSPCON2 Set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup STOP condition. Note: TBRG = one baud rate generator period. 14.4.12 CLOCK ARBITRATION 14.4.
PIC18CXX2 14.4.15 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT<4>) is set, or the bus is idle with both the S and P bits clear.
PIC18CXX2 14.4.16.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 14-24). SCL is sampled low before SDA is asserted low (Figure 14-25). b) During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 14-26).
PIC18CXX2 FIGURE 14-25: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, Bus collision occurs, set BCLIF SEN SCL = 0 before BRG time-out, Bus collision occurs, set BCLIF BCLIF Interrupt cleared in software S '0' '0' SSPIF '0' '0' FIGURE 14-26: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG Set SSPIF TBRG SDA SDA pulled low by other maste
PIC18CXX2 14.4.16.2 Bus Collision During a Repeated START Condition reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated START condition, a bus collision occurs if: a) b) If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs.
PIC18CXX2 14.4.16.3 Bus Collision During a STOP Condition The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 14-29).
PIC18CXX2 15.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full duplex) • Synchronous - Master (half duplex) • Synchronous - Slave (half duplex) In order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter: The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules.
PIC18CXX2 REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 SPEN bit 7 R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care Synchronous mode - master: 1 = Enables
PIC18CXX2 15.1 USART Baud Rate Generator (BRG) Example 15-1 shows the calculation of the baud rate error for the following conditions: The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate. In Synchronous mode, bit BRGH is ignored.
PIC18CXX2 TABLE 15-3: BAUD RATES FOR SYNCHRONOUS MODE FOSC = 40 MHz BAUD RATE (K) FOSC = 20 MHz SPBRG Actua value l Rate (decimal) (K) FOSC = 16 MHz SPBRG Actual value Rate (decimal) (K) FOSC = 10 MHz SPBRG Actual value Rate (decimal) (K) % Error SPBRG value (decimal) NA — — NA — — — NA — — — — 9.766 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 76.92 +0.16 51 75.76 -1.36 32 95.24 -0.79 41 96.15 +0.16 25 307.69 +2.56 12 312.5 +4.
PIC18CXX2 TABLE 15-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 40 MHz BAUD RATE (K) FOSC = 20 MHz FOSC = 16 MHz FOSC = 10 MHz Actual Rate (K) % Error 0.3 NA — — NA — — NA — — NA — — 1.2 NA — — 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 2.4 2.44 -1.70 255 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.
PIC18CXX2 TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) FOSC = 40 MHz BAUD RATE (K) Actual Rate (K) % Error FOSC = 20 MHz SPBRG Actual value Rate (decimal) (K) % Error FOSC = 16 MHz SPBRG Actual value Rate (decimal) (K) % Error FOSC = 10 MHz SPBRG Actual value Rate (decimal) (K) % Error SPBRG value (decimal) 64 9.6 9.77 -1.70 255 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 19.2 19.23 -0.16 129 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 38.4 38.46 -0.
PIC18CXX2 15.2 USART Asynchronous Mode data from the TXREG register (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be enabled/disabled by setting/clearing enable bit, TXIE ( PIE1<4>). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register.
PIC18CXX2 FIGURE 15-2: ASYNCHRONOUS TRANSMISSION Write to TXREG Word 1 BRG Output (shift clock) RC6/TX/CK (pin) START Bit Bit 0 TXIF bit (Transmit buffer reg. empty flag) Bit 1 Word 1 Bit 7/8 STOP Bit Word 1 Transmit Shift Reg TRMT bit (Transmit shift reg. empty flag) FIGURE 15-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG Output (shift clock) RC6/TX/CK (pin) TXIF bit (interrupt reg. flag) START Bit TRMT bit (Transmit shift reg.
PIC18CXX2 15.2.2 USART ASYNCHRONOUS RECEIVER 15.2.3 The receiver block diagram is shown in Figure 15-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate, or at FOSC. This mode would typically be used in RS-232 systems. This mode would typically be used in RS-485 systems.
PIC18CXX2 FIGURE 15-5: ASYNCHRONOUS RECEPTION START bit bit0 RX (pin) bit1 bit7/8 STOP bit Rcv shift reg Rcv buffer reg START bit bit0 START bit bit7/8 STOP bit Word 2 RCREG Word 1 RCREG Read Rcv buffer reg RCREG bit7/8 STOP bit RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC18CXX2 15.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner, (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA<4>). In addition, enable bit SPEN (RCSTA<7>) is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC18CXX2 FIGURE 15-6: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin Bit 0 Bit 1 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Bit 2 Bit 7 Word 1 Bit 0 Bit 1 Word 2 Bit 7 RC6/TX/CK pin Write to TXREG reg Write Word 1 Write Word 2 TXIF bit (Interrupt flag) TRMT bit TRMT TXEN bit Note: '1' '1' Sync Master mode; SPBRG = '0'. Continuous transmission of two 8-bit words.
PIC18CXX2 15.3.2 USART SYNCHRONOUS MASTER RECEPTION 3. 4. 5. 6. Ensure bits CREN and SREN are clear. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8.
PIC18CXX2 15.4 USART Synchronous Slave Mode Synchronous Slave mode differs from the Master mode in the fact that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA<7>). 15.4.1 USART SYNCHRONOUS SLAVE TRANSMIT To set up a Synchronous Slave Transmission: 1. 2. 3. 4. 5. 6.
PIC18CXX2 15.4.2 USART SYNCHRONOUS SLAVE RECEPTION To set up a Synchronous Slave Reception: 1. The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode and bit SREN, which is a “don't care” in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP.
PIC18CXX2 NOTES: DS39026D-page 164 1999-2013 Microchip Technology Inc.
PIC18CXX2 16.0 COMPATIBLE 10-BIT ANALOGTO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: • • • • The analog-to-digital (A/D) converter module has five inputs for the PIC18C2x2 devices and eight for the PIC18C4x2 devices. This module has the ADCON0 and ADCON1 register definitions that are compatible with the mid-range A/D module. The ADCON0 register, shown in Register 16-1, controls the operation of the A/D module.
PIC18CXX2 REGISTER 16-2: ADCON1 REGISTER R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ’0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ’0’.
PIC18CXX2 The analog reference voltage is software selectable to either the device’s positive and negative supply voltage (VDD and VSS) or the voltage level on the RA3/AN3/ VREF+ pin and RA2/AN2/VREF-. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference) or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion.
PIC18CXX2 16.1 The value that is in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ ADRESL registers will contain unknown data after a Power-on Reset. For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 16-2.
PIC18CXX2 To calculate the minimum acquisition time, Equation 16-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution.
PIC18CXX2 16.2 Selecting the A/D Conversion Clock 16.3 The ADCON1, TRISA and TRISE registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable.
PIC18CXX2 16.4 A/D Conversions 16.5 Figure 16-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers).
PIC18CXX2 TABLE 16-3: SUMMARY OF A/D REGISTERS Value on all other RESETS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR INTCON GIE/ GIEH PEIE/ GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 0000 000x 0000 000u PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 IPR1 PSPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 PI
PIC18CXX2 17.0 LOW VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do “housekeeping tasks” before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is a software programmable circuitry, where a device voltage trip point can be specified.
PIC18CXX2 FIGURE 17-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM LVDIN LVD Control Register 16 to 1 MUX VDD Internally Generated Nominal Reference Voltage 1.2V LVDEN The LVD module has an additional feature that allows the user to supply the trip voltage to the module from an external source. This mode is enabled when bits LVDL3:LVDL0 are set to 1111. In this state, the comparator input is multiplexed from the external input pin LVDIN (Figure 17-3).
PIC18CXX2 17.1 Control Register The Low Voltage Detect Control register controls the operation of the Low Voltage Detect circuitry.
PIC18CXX2 17.2 Operation The following steps are needed to set up the LVD module: Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease the current requirements, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. 1.
PIC18CXX2 17.2.1 REFERENCE VOLTAGE SET POINT The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the Programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires a time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36.
PIC18CXX2 NOTES: DS39026D-page 178 1999-2013 Microchip Technology Inc.
PIC18CXX2 18.0 SPECIAL FEATURES OF THE CPU There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC18CXX2 REGISTER 18-1: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 300001h) R/P-1 R/P-1 R/P-1 U-0 U-0 R/P-1 R/P-1 R/P-1 Reserved Reserved OSCSEN — — FOSC2 FOSC1 FOSC0 bit 7 bit 0 bit 7-6 Reserved: Read as ’1’ bit 5 OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (main oscillator is source) 0 = Oscillator system clock switch option is enabled (oscillator switching is enabled) bit 4-3 Unimplemented: Read as ’0’ bit 2-
PIC18CXX2 REGISTER 18-3: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 300003h) U-0 U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 — — — — WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 bit 7-4 Unimplemented: Read as ’0’ bit 3-1 WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 111 = 1:1 110 = 1:2 101 = 1:4 100 = 1:8 011 = 1:16 010 = 1:32 001 = 1:64 000 = 1:128 bit 0 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bi
PIC18CXX2 REGISTER 18-5: CONFIGURATION REGISTER 3 HIGH (CONFIG3H: BYTE ADDRESS 300005h) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/P-1 — — — — — — — CCP2MX bit 7 bit 0 bit 7-1 Unimplemented: Read as ’0’ bit 0 CCP2MX: CCP2 Mux bit 1 = CCP2 input/output is multiplexed with RC1 0 = CCP2 input/output is multiplexed with RB3 Legend: R = Readable bit P = Programmable bit - n = Value when device is unprogrammed REGISTER 18-6: U = Unimplemented bit, read as ‘0’ u = Unchanged from programmed state CONF
PIC18CXX2 18.2 Watchdog Timer (WDT) The Watchdog Timer is a free running, on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/ CLKO/RA6 pins of the device has been stopped, for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset).
PIC18CXX2 18.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of device programming, by the value written to the CONFIG2H configuration register. FIGURE 18-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8 - to - 1 MUX WDTEN Configuration bit WDTPS2:WDTPS0 SWDTEN bit WDT Time-out Note: TABLE 18-2: WDPS2:WDPS0 are bits in register CONFIG2H.
PIC18CXX2 18.3 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared, but keeps running, the PD bit (RCON<3>) is cleared, the TO (RCON<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC18CXX2 WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) FIGURE 18-2: Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKOUT(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(3) GIEH bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: 18.4 PC PC+2 Inst(PC) = SLEEP Inst(PC + 2) Inst(PC + 4) SLEEP Inst(PC + 2) Inst(PC - 1) PC+4 18.
PIC18CXX2 19.0 INSTRUCTION SET SUMMARY The PIC18CXXX instruction set adds many enhancements to the previous PIC instruction sets, while maintaining an easy migration from these PIC MCU instruction sets. Most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations.
PIC18CXX2 TABLE 19-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7) BSR Bank Select Register. Used to select the current RAM bank. d Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f.
PIC18CXX2 FIGURE 19-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 ADDWF MYREG, W, B f (FILE #) d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f = 12-bi
PIC18CXX2 TABLE 19-2: PIC18CXXX INSTRUCTION SET Mnemonic, Operands 16-bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF 1 f, d, a Add WREG and f 0010 01da ffff ffff C, DC, Z, OV, N 1, 2 ADDWFC f, d, a Add WREG and Carry bit to f 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2 ANDWF 1 f, d, a AND WREG with f 1,2 0001 01da ffff ffff Z, N Clear f CLRF 1 f, a 2 0110 101a ffff ffff Z COMF 1 f, d, a Complement f 1, 2 0001 11da ffff ffff Z, N Comp
PIC18CXX2 TABLE 19-2: Mnemonic, Operands PIC18CXXX INSTRUCTION SET (CONTINUED) 16-bit Instruction Word Description CONTROL OPERATIONS BC n Branch if Carry BN n Branch if Negative BNC n Branch if Not Carry BNN n Branch if Not Negative BNOV n Branch if Not Overflow BNZ n Branch if Not Zero BOV n Branch if Overflow BRA n Branch Unconditionally BZ n Branch if Zero CALL n, s Call subroutine1st word 2nd word CLRWDT — Clear Watchdog Timer DAW — Decimal Adjust WREG GOTO n Go to address1st word 2nd word NOP — No O
PIC18CXX2 TABLE 19-2: PIC18CXXX INSTRUCTION SET (CONTINUED) Mnemonic, Operands 16-bit Instruction Word Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Move literal (12-bit) 2nd word 2 1110 1110 00ff kkkk None to FSRx 1st word 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 000
PIC18CXX2 19.
PIC18CXX2 ADDWFC ADD WREG and Carry bit to f ANDLW AND literal with WREG Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a] Operation: (WREG) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: ffff 1 Cycles: 1 Operands: 0 k 255 Operation: (WREG) .AND. k WREG Status Affected: N,Z Encoding: ffff Add WREG, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in WREG.
PIC18CXX2 ANDWF AND WREG with f Syntax: [ label ] ANDWF Operands: 0 f 255 d [0,1] a [0,1] f [,d [,a] Operation: (WREG) .AND. (f) dest Status Affected: N,Z Encoding: 0001 BC Branch if Carry Syntax: [ label ] BC Operands: -128 n 127 Operation: if carry bit is ’1’ (PC) + 2 + 2n PC Status Affected: None Encoding: 01da ffff ffff 1110 n 0010 nnnn nnnn Description: Description: The contents of WREG are AND’ed with register 'f'.
PIC18CXX2 BCF Bit Clear f Syntax: [ label ] BCF Operands: 0 f 255 0b7 a [0,1] Operation: 0 f Status Affected: None Encoding: 1001 Description: Branch if Negative Syntax: [ label ] BN Operands: -128 n 127 Operation: if negative bit is ’1’ (PC) + 2 + 2n PC Status Affected: None Encoding: bbba ffff ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: BCF Before Instruction FLAG_REG = 0xC7 After Instruc
PIC18CXX2 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: [ label ] BNC Syntax: [ label ] BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if carry bit is ’0’ (PC) + 2 + 2n PC Operation: if negative bit is ’0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 n 0011 nnnn nnnn Encoding: 1110 n 0111 nnnn nnnn Description: If the Carry bit is ’0’, then the program will branch.
PIC18CXX2 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: [ label ] BNOV Syntax: [ label ] BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if overflow bit is ’0’ (PC) + 2 + 2n PC Operation: if zero bit is ’0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: 1110 n 0101 nnnn nnnn Encoding: 1110 n 0001 nnnn nnnn Description: If the Overflow bit is ’0’, then the program will branch.
PIC18CXX2 BRA Unconditional Branch BSF Bit Set f Syntax: [ label ] BRA Syntax: [ label ] BSF Operands: -1024 n 1023 Operands: Operation: (PC) + 2 + 2n PC Status Affected: None 0 f 255 0b7 a [0,1] Operation: 1 f Status Affected: None Encoding: Description: 1101 1 Cycles: 2 Q Cycle Activity: Q1 No operation 0nnn nnnn nnnn Add the 2’s complement number ’2n’ to the PC.
PIC18CXX2 BTFSC Bit Test File, Skip if Clear BTFSS Bit Test File, Skip if Set Syntax: [ label ] BTFSC f,b[,a] Syntax: [ label ] BTFSS f,b[,a] Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Encoding: 1010 bbba ffff ffff Description: If bit 'b' in register ’f' is 0, then the next instruction is skipped.
PIC18CXX2 BTG Bit Toggle f BOV Branch if Overflow Syntax: [ label ] BTG f,b[,a] Syntax: [ label ] BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if overflow bit is ’1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: ffff 1 Cycles: 1 Q Cycle Activity: Q1 Q2 Q3 Q4 Read register 'f' Process Data Write register 'f' Example: BTG PORTC, = 0111 0101 [0x75] After Instruction: POR
PIC18CXX2 BZ Branch if Zero CALL Subroutine Call Syntax: [ label ] BZ Syntax: [ label ] CALL k [,s] Operands: -128 n 127 Operands: Operation: if Zero bit is ’1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (WREG) WS, (STATUS) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the Zero bit is ’1’, then the program will branch.
PIC18CXX2 CLRF Clear f Syntax: [label] CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: Description: 0110 f [,a] 101a ffff ffff CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 000h WDT, 000h WDT postscaler, 1 TO, 1 PD Status Affected: TO, PD Encoding: 0000 0000 0000 0100 Clears the contents of the specified register. If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value.
PIC18CXX2 COMF Syntax: [ label ] COMF Operands: 0 f 255 d [0,1] a [0,1] Operation: ( f ) dest Status Affected: N,Z Encoding: 0001 Description: 1 Cycles: 1 Q Cycle Activity: Q1 ffff [ label ] CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (WREG), skip if (f) = (WREG) (unsigned comparison) Status Affected: None Encoding: 0110 001a f [,a] ffff ffff Description: Compares the contents of data memory location 'f' to the contents of WREG by performing an unsigned su
PIC18CXX2 CPFSGT Compare f with WREG, skip if f > WREG CPFSLT Syntax: [ label ] CPFSGT Syntax: [ label ] CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) WREG), skip if (f) > (WREG) (unsigned comparison) Operation: (f) –WREG), skip if (f) < (WREG) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0110 010a f [,a] Compare f with WREG, skip if f < WREG ffff ffff Compares the contents of data memory locat
PIC18CXX2 DAW Decimal Adjust WREG Register DECF Decrement f Syntax: [label] DAW Syntax: [ label ] DECF f [,d [,a] Operands: None Operands: Operation: If [WREG<3:0> >9] or [DC = 1] then (WREG<3:0>) + 6 WREG<3:0>; else (WREG<3:0>) WREG<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C,DC,N,OV,Z If [WREG<7:4> >9] or [C = 1] then (WREG<7:4>) + 6 WREG<7:4>; else (WREG<7:4>) WREG<7:4>; Status Affected: 0000 Encoding: 0000 0000 0000 Words: 1 Cycles
PIC18CXX2 DECFSZ Decrement f, skip if 0 DCFSNZ Decrement f, skip if not 0 Syntax: [ label ] DECFSZ f [,d [,a]] Syntax: [label] DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 11da ffff ffff Encoding: 0100 11da f [,d [,a] ffff ffff Description: The contents of register 'f' are decrement
PIC18CXX2 GOTO Unconditional Branch INCF Increment f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C,DC,N,OV,Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 GOTO k 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch anywhere within entire 2 Mbyte memory range.
PIC18CXX2 INCFSZ Increment f, skip if 0 INFSNZ Increment f, skip if not 0 Syntax: [ label ] Syntax: [label] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 INCFSZ 11da f [,d [,a] ffff ffff Encoding: 0100 INFSNZ 10da f [,d [,a] ffff ffff Description: The contents of register 'f' are increme
PIC18CXX2 IORLW Inclusive OR literal with WREG IORWF Inclusive OR WREG with f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: (WREG) .OR. k WREG Status Affected: N,Z 0 f 255 d [0,1] a [0,1] Operation: (WREG) .OR.
PIC18CXX2 LFSR Load FSR MOVF Move f Syntax: [ label ] Syntax: [ label ] Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N,Z Encoding: LFSR f,k 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal 'k' is loaded into the file select register pointed to by 'f'.
PIC18CXX2 MOVFF Move f to f MOVLB Move literal to low nibble in BSR Syntax: [label] Syntax: [ label ] Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR None MOVFF fs,fd Operation: (fs) fd Status Affected: Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register 'fs' are moved to destination register 'fd'.
PIC18CXX2 MOVLW Move literal to WREG MOVWF Move WREG to f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: Operation: k WREG 0 f 255 a [0,1] Status Affected: None Operation: (WREG) f Status Affected: None Encoding: 0000 Description: MOVLW k 1110 kkkk The eight-bit literal 'k' is loaded into WREG.
PIC18CXX2 MULLW Multiply Literal with WREG MULWF Multiply WREG with f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 a [0,1] Operation: (WREG) x (f) PRODH:PRODL Status Affected: None MULLW k Operands: 0 k 255 Operation: (WREG) x k PRODH:PRODL Status Affected: None Encoding: Description: 0000 1 Cycles: 1 Q Cycle Activity: Q1 Example: kkkk kkkk An unsigned multiplication is carried out between the contents of WREG and the 8-bit literal 'k'.
PIC18CXX2 NEGF Negate f Syntax: [label] Operands: 0 f 255 a [0,1] NEGF f [,a] Operation: (f)+1f Status Affected: N,OV, C, DC, Z Encoding: 0110 Description: 1 Cycles: 1 Q Cycle Activity: Q1 Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None 0000 1111 ffff Description: 1 Cycles: 1 Decode 0000 xxxx 0000 xxxx No operation.
PIC18CXX2 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: [ label ] Syntax: [ label ] Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC+2) TOS Status Affected: None Status Affected: None Encoding: 0000 Description: 0000 0000 0110 The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18CXX2 RCALL Relative Call RESET Reset Syntax: [ label ] RCALL Syntax: [ label ] Operands: Operation: -1024 n 1023 Operands: None (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR reset. Status Affected: None Status Affected: All Encoding: 1101 Description: 1nnn n nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack.
PIC18CXX2 RETFIE Return from Interrupt RETLW Return Literal to WREG Syntax: [ label ] Syntax: [ label ] RETFIE [s] RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) WREG, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged.
PIC18CXX2 RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RETURN [s] RLCF f [,d [,a] Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) WREG, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C,N,Z None Encoding: Status Affected: Encoding: 0000 0000 0001 001s Description: Return from subroutine
PIC18CXX2 RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N,Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C,N,Z Encoding: 0100 Description: RLNCF 01da f [,d [,a] ffff ffff The contents of register 'f' are rotated one bit to the left.
PIC18CXX2 RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [label] SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) dest, (f<0>) dest<7> FFh f Operation: Status Affected: None Status Affected: N,Z Encoding: 0100 Description: RRNCF 00da f [,d [,a] Encoding: ffff ffff The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in WREG.
PIC18CXX2 SLEEP Enter SLEEP mode SUBFWB Subtract f from WREG with borrow Syntax: [ label ] SLEEP Syntax: [ label ] SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (WREG) – (f) – (C) dest Status Affected: N,OV, C, DC, Z TO, PD Encoding: Status Affected: Encoding: 0000 0000 0000 0011 Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set.
PIC18CXX2 SUBLW Subtract WREG from literal SUBWF Subtract WREG from f Syntax: [ label ] SUBLW k Syntax: [ label ] SUBWF Operands: 0 k 255 Operands: Operation: k – (WREG) WREG Status Affected: N,OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Encoding: 0000 Description: 1000 kkkk kkkk WREG is subtracted from the eight-bit literal 'k'. The result is placed in WREG.
PIC18CXX2 SUBWFB Subtract WREG from f with Borrow SWAPF Swap f Syntax: [ label ] SUBWFB Syntax: [ label ] SWAPF f [,d [,a] Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (WREG) – (C) dest Operation: Status Affected: N,OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: ffff ffff Subtract WREG and the carry flag (borrow) from register 'f' (2’s complement method).
PIC18CXX2 TBLRD Table Read TBLRD Table Read (cont’d) Syntax: [ label ] Example 1: TBLRD TBLRD ( *; *+; *-; +*) Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Status Affected: Description: Before Instruction 0000 TABLAT TBLPTR MEMORY(0x00A356) 0000 0000 = =
PIC18CXX2 TBLWT Table Write TBLWT Table Write (Continued) Syntax: [ label ] Example 1: TBLWT TBLWT ( *; *+; *-; +*) Operands: None Operation: if TBLWT*, (TABLAT) Prog Mem (TBLPTR) or Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Prog Mem (TBLPTR) or Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Prog Mem (TBLPTR) or Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Prog Mem (TBLPTR) or Holding Register; Status Affected: *+; B
PIC18CXX2 TSTFSZ Test f, skip if 0 XORLW Exclusive OR literal with WREG Syntax: [ label ] TSTFSZ f [,a] Syntax: [ label ] XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: skip if f = 0 Operation: (WREG) .XOR.
PIC18CXX2 XORWF Exclusive OR WREG with f Syntax: [ label ] XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (WREG) .XOR. (f) dest Status Affected: N,Z Encoding: 0001 10da f [,d [,a] ffff ffff Description: Exclusive OR the contents of WREG with register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in the register 'f' (default). If ‘a’ is 0, the Access Bank will be selected, overriding the BSR value.
PIC18CXX2 20.
PIC18CXX2 20.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC18CXX2 20.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC16F87X and can be used to develop for this and other PIC microcontrollers from the PIC16CXXX family. The MPLAB ICD utilizes the in-circuit debugging capability built into the PIC16F87X.
PIC18CXX2 20.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X 1999-2013 Microchip Technology Inc. † † * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
PIC18CXX2 NOTES: DS39026D-page 234 1999-2013 Microchip Technology Inc.
PIC18CXX2 21.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ....................................... -0.
PIC18CXX2 FIGURE 21-1: PIC18CXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0 V 5.5 V 5.0 V PIC18CXXX Voltage 4.5 V 4.2V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 40 MHz Frequency FIGURE 21-2: PIC18LCXX2 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0 V 5.5 V Voltage 5.0 V PIC18LCXXX 4.5 V 4.2V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 40 MHz 6 MHz Frequency FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz Note: VDDAPPMIN is the minimum voltage of the PIC® device in the application.
PIC18CXX2 21.1 DC Characteristics PIC18LCXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18CXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol Characteristic Min Typ Max Units Conditions Supply Voltage PIC18LCXX2 2.5 — 5.5 V HS, XT, RC and LP osc mode PIC18CXX2 4.2 — 5.
PIC18CXX2 21.1 DC Characteristics (Continued) PIC18LCXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18CXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18CXX2 21.1 DC Characteristics (Continued) PIC18LCXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial PIC18CXX2 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No. Symbol IPD D020 Characteristic Min Typ Max Units Conditions Power-down Current(3) — <.5 2 A VDD = 2.
PIC18CXX2 21.2 DC Characteristics: PIC18CXX2 (Industrial, Extended) PIC18LCXX2 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VIL D030 D030A D031 D032 D032A D033 VIH D040 Characteristic Min Max Units Vss — Vss Vss VSS VSS 0.15VDD 0.8 0.2VDD 0.3VDD 0.2VDD 0.3VDD V V V V V V VSS 0.2VDD V 0.25VDD + 0.8V 2.0 VDD V VDD < 4.5V VDD V 4.5V VDD 5.
PIC18CXX2 21.2 DC Characteristics: PIC18CXX2 (Industrial, Extended) PIC18LCXX2 (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended DC CHARACTERISTICS Param Symbol No. VOL D080 Characteristic Output Low Voltage I/O ports D080A D083 OSC2/CLKOUT (RC mode) D083A VOH D090 Output High Voltage(3) I/O ports D090A D092 OSC2/CLKOUT (RC mode) D092A Min Max Units — 0.6 V — 0.
PIC18CXX2 FIGURE 21-3: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 21-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for extended Param No.
PIC18CXX2 TABLE 21-2: EPROM PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +40°C DC CHARACTERISTICS Param. No.
PIC18CXX2 21.3 21.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2.
PIC18CXX2 21.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 21-3 apply to all timing specifications unless otherwise noted. Figure 21-4 specifies the load conditions for the timing specifications.
PIC18CXX2 21.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 21-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKOUT TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. Symbol 1A 1 2 3 FOSC TOSC TCY TosL, TosH Min Max Units External CLKIN Frequency(1) Characteristic DC DC 4 DC DC 4 25 10 40 40 MHz MHz MHz kHz MHz XT osc HS osc HS + PLL osc LP osc EC, ECIO Conditions Oscillator Frequency(1) DC 0.
PIC18CXX2 TABLE 21-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V) Param Symbol No. Characteristic Min Max Units TRC PLL Start-up Time (Lock Time) — 2 ms CLK CLKOUT Stability (Jitter) using PLL -2 +2 % FIGURE 21-6: Conditions CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 14 19 12 18 16 I/O Pin (input) 15 17 I/O Pin (output) new value old value 20, 21 Note: Refer to Figure 21-4 for load conditions. TABLE 21-6: Param. No.
PIC18CXX2 FIGURE 21-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 21-4 for load conditions. FIGURE 21-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.
PIC18CXX2 FIGURE 21-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 41 40 42 T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 21-4 for load conditions. TABLE 21-8: Param No.
PIC18CXX2 FIGURE 21-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) 50 51 52 CCPx (Compare or PWM Mode) 53 Note: TABLE 21-9: 54 Refer to Figure 21-4 for load conditions. CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param. Symbol No. Characteristic Min Max Units 0.5TCY + 20 10 20 0.
PIC18CXX2 FIGURE 21-11: PARALLEL SLAVE PORT TIMING (PIC18C4X2) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 21-4 for load conditions. TABLE 21-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C4X2) Param. No.
PIC18CXX2 FIGURE 21-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 21-4 for load conditions. TABLE 21-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No.
PIC18CXX2 FIGURE 21-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 21-4 for load conditions. TABLE 21-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No.
PIC18CXX2 FIGURE 21-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 21-4 for load conditions. TABLE 21-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)) Param. No.
PIC18CXX2 FIGURE 21-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN 77 BIT6 - - - -1 LSb IN 74 Note: Refer to Figure 21-4 for load conditions. TABLE 21-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No.
PIC18CXX2 FIGURE 21-16: I2C BUS START/STOP BITS TIMING SCL 91 93 90 92 SDA STOP Condition START Condition Note: Refer to Figure 21-4 for load conditions. TABLE 21-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18CXX2 FIGURE 21-17: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 107 91 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 21-4 for load conditions. TABLE 21-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 101 102 103 90 91 106 107 92 109 110 D102 Symbol THIGH TLOW TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF CB Characteristic Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time Min Max Units 100 kHz mode 4.
PIC18CXX2 FIGURE 21-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 21-4 for load conditions. TABLE 21-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18CXX2 FIGURE 21-19: MASTER SSP I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 91 92 107 SDA In 109 110 109 SDA Out Note: Refer to Figure 21-4 for load conditions. TABLE 21-18: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol No.
PIC18CXX2 FIGURE 21-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 Note: 122 Refer to Figure 21-4 for load conditions. TABLE 21-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No.
PIC18CXX2 TABLE 21-21: A/D CONVERTER CHARACTERISTICS: PIC18CXX2 (INDUSTRIAL, EXTENDED) PIC18LCXX2 (INDUSTRIAL) Param Symbol No. Characteristic Min Typ Max Units bit bit Conditions VREF = VDD 3.0V VREF = VDD 3.0V A01 NR Resolution — — — — 10 10 A03 EIL Integral linearity error — — — — <±1 <±2 LSb VREF = VDD 3.0V LSb VREF = VDD 3.0V A04 EDL Differential linearity error — — — — <±1 <±2 LSb VREF = VDD 3.0V LSb VREF = VDD 3.
PIC18CXX2 FIGURE 21-22: A/D CONVERSION TIMING BSF ADCON0, GO Note 2 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 ... ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18CXX2 22.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES The graphs and tables provided in this section are for design guidance and are not tested. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time and matrix samples. 'Typical' represents the mean of the distribution at 25C. 'Max' or 'min' represents (mean + 3) or (mean - 3) respectively, where is standard deviation, over the whole temperature range.
PIC18CXX2 FIGURE 22-3: TYPICAL IDD vs. FOSC OVER VDD (HS/PLL MODE) 25 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 20 IDD (mA) 15 5.5V 5.0V 10 4.5V 4.0V 3.5V 3.0V 5 2.5V 0 4 5 6 7 8 9 10 9 10 FOSC (MHz) MAXIMUM IDD vs. FOSC OVER VDD (HS/PLL MODE) FIGURE 22-4: 25 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 20 5.5V 5.0V IDD (mA) 15 4.5V 4.0V 10 3.5V 3.0V 5 2.
PIC18CXX2 FIGURE 22-5: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.0 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 0.8 5.0V IDD (mA) 0.6 4.5V 0.4 4.0V 0.2 3.5V 3.0V 2.5V 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 FOSC (MHz) FIGURE 22-6: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.5 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.0 5.0V 4.5V IDD (mA) 1.5 4.
PIC18CXX2 FIGURE 22-7: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 200 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 180 IDD (uA) 160 140 5.5V 120 5.0V 100 4.5V 80 4.0V 60 3.5V 3.0V 40 2.5V 20 0 20 30 40 50 60 70 80 90 100 80 90 100 FOSC (kHz) FIGURE 22-8: MAXIMUM IDD vs.
PIC18CXX2 FIGURE 22-9: TYPICAL AND MAXIMUM IDD vs. VDD (TIMER1 AS MAIN OSCILLATOR, 32.768 kHz, C = 47 pF) 300 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 250 200 IDD (uA) Max (-40C) 150 Typ (25C) 100 50 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 22-10: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, 25C) 4.0 3.5 3.3k 3.0 2.5 Freq (MHz) 5.1k 2.0 1.5 10k 1.0 0.5 100k 0.0 2.5 3.0 3.
PIC18CXX2 FIGURE 22-11: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, 25C) 1.8 1.6 3.3k 1.4 1.2 Freq (MHz) 5.1k 1.0 0.8 0.6 10k 0.4 0.2 100k 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 5.0 5.5 VDD (V) FIGURE 22-12: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, 25C) 1.0 0.9 0.8 3.3k 0.7 Freq (MHz) 0.6 5.1k 0.5 0.4 0.3 10k 0.2 0.1 100k 0.0 2.5 3.0 3.5 4.0 4.5 V DD (V) DS39026D-page 268 1999-2013 Microchip Technology Inc.
PIC18CXX2 FIGURE 22-13: IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED) 100.00 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Max (125C) 10.00 I PD (uA) Max (85C) 1.00 Typ (25C) 0.10 0.01 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 22-14: IBOR vs. VDD OVER TEMPERATURE (BOR ENABLED, VBOR = 2.50V - 2.
PIC18CXX2 FIGURE 22-15: TYPICAL AND MAXIMUMITMR1 vs. VDD OVER TEMPERATURE (-40C TO +125C, TIMER1 WITH OSCILLATOR, XTAL=32 kHZ, C1 AND C2 = 47 pF) 90 80 Max (-40C to 125C) Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 70 I TMR1OSC ( A) 60 50 Typ (25C) 40 30 20 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) TYPICAL AND MAXIMUM IWDT vs. VDD OVER TEMPERATURE (WDT ENABLED) FIGURE 22-16: 4.0 3.
PIC18CXX2 FIGURE 22-17: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C) 60 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 50 WDT Period (ms) 40 Max (125C) 30 20 Typ (25C) Min (-40C) 10 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 22-18: ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 3.0V - 3.
PIC18CXX2 FIGURE 22-19: ILVD vs. VDD OVER TEMPERATURE (LVD ENABLED, VLVD = 4.5V - 4.78V) 45 Max (125C) Max (125C) 40 Typ (25C) Typ (25C) 35 I LVD ( A) 30 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 25 LVDIF is unknown 20 LVDIF can be cleared by firmware 15 LVDIF is set by hardware 10 5 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 22-20: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.0 4.
PIC18CXX2 FIGURE 22-21: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 2.5 Max (-40C) Typ (25C) 2.0 VOH (V) Min (125C) 1.5 1.0 0.5 0.0 0 5 10 15 20 25 I OH (-mA) FIGURE 22-22: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1.4 1.2 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.
PIC18CXX2 FIGURE 22-23: TYPICAL AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 2.4 2.2 2.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.8 1.6 VOL (V) 1.4 1.2 Max (-40C to 125C) 1.0 0.8 0.6 Typ (25C) 0.4 0.2 0.0 0 5 10 15 20 25 IOL (mA) FIGURE 22-24: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40C TO +125C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 3.
PIC18CXX2 FIGURE 22-25: MINIMUM AND MAXIMUM VIN vs. VDD, (TTL INPUT, -40C TO +125C) 2.0 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3 (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) 1.6 1.4 Max VTH (-40C) VIN (V) 1.2 1.0 Min VTH (125C) 0.8 0.6 0.4 0.2 0.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V) FIGURE 22-26: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40C TO +125C) 4.0 Min V IH (-40C) Max VIH (125C) 3.
PIC18CXX2 NOTES: DS39026D-page 276 1999-2013 Microchip Technology Inc.
PIC18CXX2 23.0 PACKAGING INFORMATION 23.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC 0117017 Example XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Legend: XX...
PIC18CXX2 Package Marking Information (Cont’d) Example 40-Lead PDIP XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 28- and 40-Lead JW (CERDIP) PIC18C442-I/P 0112017 Example PIC18C452 -I/JW XXXXXXXXXXX XXXXXXXXXXX XXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS39026D-page 278 0115017 Example PIC18C442 -E/PT 0120017 Example PIC18C452 -I/L 0120017 1999-2013 Microchip Technology Inc.
PIC18CXX2 23.2 Package Details The following sections give the technical details of the packages. 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 E A2 A L c B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .
PIC18CXX2 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC18CXX2 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 1 n E A2 A L c B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.
PIC18CXX2 28-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W D 2 n 1 E A2 A L c eB Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC18CXX2 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil (CERDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 W D 2 1 n E A2 A A1 c B1 B eB Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Ceramic Package Height Standoff Shoulder to Shoulder Width Ceramic Pkg.
PIC18CXX2 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC18CXX2 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 1 2 CH2 x 45 CH1 x 45 A3 A2 35 A B1 B c E2 Units Dimension Limits n p A1 p D2 INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .
PIC18CXX2 NOTES: DS39026D-page 286 1999-2013 Microchip Technology Inc.
PIC18CXX2 APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (July 1999) DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table 1. Original data sheet for PIC18CXX2 family. Revision B (March 2001) Added DC and (Section 22.0). AC characteristics graphs Revision C (January 2013) Added a note to each package outline drawing.
PIC18CXX2 APPENDIX C: CONVERSION CONSIDERATIONS This appendix discusses the considerations for converting from previous versions of a device to the ones listed in this data sheet. Typically, these changes are due to the differences in the process technology used. An example of this type of conversion is from a PIC16C74A to a PIC16C74B. Not Applicable DS39026D-page 288 APPENDIX D: MIGRATION FROM BASELINE TO ENHANCED DEVICES This section discusses how to migrate from a Baseline device (i.e.
PIC18CXX2 APPENDIX E: MIGRATION FROM MID-RANGE TO ENHANCED DEVICES A detailed discussion of the differences between the mid-range MCU devices (i.e., PIC16CXXX) and the enhanced devices (i.e., PIC18CXXX) is provided in AN716, “Migrating Designs from PIC16C74A/74B to PIC18C442.” The changes discussed, while device specific, are generally applicable to all mid-range to enhanced device migrations.
PIC18CXX2 NOTES: DS39026D-page 290 1999-2013 Microchip Technology Inc.
PIC18CXX2 INDEX A A/D ................................................................................... 165 A/D Converter Flag (ADIF Bit) ................................. 167 A/D Converter Interrupt, Configuring ....................... 168 ADCON0 Register .................................................... 165 ADCON1 Register ............................................ 165, 166 ADRES Register .............................................. 165, 167 Analog Port Pins ......................................
PIC18CXX2 Code Examples 16 x 16 Signed Multiply Routine ................................ 62 16 x 16 Unsigned Multiply Routine ............................ 62 8 x 8 Signed Multiply Routine .................................... 61 8 x 8 Unsigned Multiply Routine ................................ 61 Changing Between Capture Prescalers ................... 109 Fast Register Stack .................................................... 39 Initializing PORTA ......................................................
PIC18CXX2 Instruction Set .................................................................. 187 ADDLW .................................................................... 193 ADDWF .................................................................... 193 ADDWFC ................................................................. 194 ANDLW .................................................................... 194 ANDWF .................................................................... 195 BC ...................
PIC18CXX2 M Master Synchronous Serial Port (MSSP). See SSP. Memory Organization Data Memory ............................................................. 42 Program Memory ....................................................... 35 Migration from Baseline to Enhanced Devices ................ 288 MOVF ............................................................................... 211 MOVFF ............................................................................. 212 MOVLB .................................
PIC18CXX2 PORTC Associated Registers ................................................. 84 Block Diagram (Peripheral Output Override) ............. 83 Initialization .......................................................... 83, 85 PORTC Register ........................................................ 83 RC3/SCK/SCL Pin ................................................... 129 RC7/RX/DT Pin ........................................................ 151 TRISC Register ............................................
PIC18CXX2 S T SCI. See USART. SCK .................................................................................. 121 SDI ................................................................................... 121 SDO ................................................................................. 121 Serial Clock, SCK ............................................................. 121 Serial Communication Interface. See USART Serial Data In, SDI ...........................................................
PIC18CXX2 STOP Condition Receive or Transmit ...................... 143 Time-out Sequence on Power-up ........................ 32, 33 USART Asynchronous Master Transmission ........... 156 USART Asynchronous Reception ............................ 158 USART Synchronous Reception .............................. 161 USART Synchronous Transmission ........................ 160 Wake-up from SLEEP via Interrupt .......................... 186 Timing Diagrams and Specifications ................................
PIC18CXX2 NOTES: DS39026D-page 298 1999-2013 Microchip Technology Inc.
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PIC18CXX2 PIC18CXX2 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device X Temperature Range /XX XXX Package Pattern PIC18CXX2(1), PIC18CXX2T(2); VDD range 4.2V to 5.5V PIC18LCXX2(1), PIC18LCXX2T(2); VDD range 2.5V to 5.
PIC18CXX2 DS39026D-page 302 1999-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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