Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 59
PIC18CXX2
5.2.3 INTERRUPTS
The long write must be terminated by a RESET or any
interrupt.
The interrupt source must have its interrupt enable bit
set. When the source sets its interrupt flag, program-
ming will terminate. This will occur, regardless of the
settings of interrupt priority bits, the GIE/GIEH bit, or
the PIE/GIEL bit.
Depending on the states of interrupt priority bits, the
GIE/GIEH bit or the PIE/GIEL bit, program execution
can either be vectored to the high or low priority Inter-
rupt Service Routine (ISR), or continue execution from
where programming commenced.
In either case, the interrupt flag will not be cleared
when programming is terminated and will need to be
cleared by the software.
TABLE 5-2: LONG WRITE EXECUTION, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS
5.2.4 UNEXPECTED TERMINATION OF
WRITE OPERATIONS
If a write is terminated by an unplanned event such as
loss of power, an unexpected RESET, or an interrupt
that was not disabled, the memory location just pro-
grammed should be verified and reprogrammed if
needed.
GIE/
GIEH
PIE/
GIEL
Priority
Interrupt
Enable
Interrupt
Flag
Action
XX X
0
(default)
X
Long write continues
even if interrupt flag becomes set.
XX X 1 0
Long write continues, will resume operations
when the interrupt flag is set.
0
(default)
0
(default)
X11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default)
1
1
high priority
(default)
11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
1
0
(default)
0
low
11
Terminates long write, executes next instruction.
Interrupt flag not cleared.
0
(default)
1
0
low
11
Terminates long write,
branches to low priority interrupt vector.
Interrupt flag can be cleared by ISR.
1
0
(default)
1
high priority
(default)
11
Terminates long write,
branches to high priority interrupt vector.
Interrupt flag can be cleared by ISR.