Datasheet
1999-2013 Microchip Technology Inc. DS39026D-page 31
PIC18CXX2
TRISE 242 442 252 452 0000 -111 0000 -111 uuuu -uuu
TRISD 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISC 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISB 242 442 252 452 1111 1111 1111 1111 uuuu uuuu
TRISA
(5, 7)
242 442 252 452 -111 1111
(5)
-111 1111
(5)
-uuu uuuu
(5)
LATE 242 442 252 452 ---- -xxx ---- -uuu ---- -uuu
LATD 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
LATA
(5, 7)
242 442 252 452 -xxx xxxx
(5)
-uuu uuuu
(5)
-uuu uuuu
(5)
PORTE 242 442 252 452 ---- -000 ---- -000 ---- -uuu
PORTD
242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTC 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTB 242 442 252 452 xxxx xxxx uuuu uuuu uuuu uuuu
PORTA
(5, 7)
242 442 252 452 -x0x 0000
(5)
-u0u 0000
(5)
-uuu uuuu
(5)
TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets
WDT Reset
RESET Instruction
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the hard-
ware stack.
4: See Table 3-2 for RESET value for specific condition.
5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other
oscillator modes, they are disabled and read ’0’.
6: The long write enable is only reset on a POR or MCLR
Reset.
7: Bit 6 of PORTA, LATA and TRISA are not available on all devices. When unimplemented, they are read as ’0’.