Datasheet

PIC18CXX2
DS39026D-page 262  1999-2013 Microchip Technology Inc.
FIGURE 21-22: A/D CONVERSION TIMING
TABLE 21-22: A/D CONVERSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
130 T
AD A/D clock period PIC18CXXX 1.6 20
(5)
sTOSC based, VREF  3.0V
PIC18LCXXX 3.0 20
(5)
sTOSC based, VREF full range
PIC18CXXX 2.0 6.0 s A/D RC mode
PIC18LCXXX 3.0 9.0 s A/D RC mode
131 T
CNV Conversion time
(not including acquisition time) (Note 1)
11 12 TAD
132 TACQ Acquisition time (Note 3) 15
10
—
—
s
s
-40C  Temp  125C
0C  Temp  125C
135 T
SWC Switching Time from convert  sample — (Note 4)
136 T
AMP Amplifier settling time (Note 2) 1—s This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on C
HOLD).
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 16.0 for minimum conditions, when input voltage has changed more than 1 LSb.
3: The time for the holding capacitor to acquire the “New” input voltage, when the voltage changes full scale
after the conversion (AV
DD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is
50 .
4: On the next Q4 cycle of the device clock.
5: The time of the A/D clock period is dependent on the device frequency and the T
AD clock divider.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
Note 2
987 21 0
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts.
This allows the SLEEP instruction to be executed.
2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
. . .
. . .
TCY