Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 253
PIC18CXX2
FIGURE 21-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 21-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 21-4 for load conditions.
Param.
No.
Symbol Characteristic Min Max Units Conditions
71 TscH SCK input high time
(Slave mode)
Continuous 1.25T
CY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 TscL SCK input low time
(Slave mode)
Continuous 1.25T
CY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73 TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100 — ns
73A T
B2B Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5T
CY + 40 — ns (Note 2)
74 TscH2diL,
Tsc L2 di L
Hold time of SDI data input to SCK edge
100 — ns
75 TdoR SDO data output rise time PIC18CXXX — 25 ns
PIC18LCXXX 45 ns
76 TdoF SDO data output fall time — 25 ns
78 TscR SCK output rise time
(Master mode)
PIC18CXXX — 25 ns
PIC18LCXXX 45 ns
79 TscF SCK output fall time (Master mode) — 25 ns
80 TscH2doV,
TscL2doV
SDO data output valid after
SCK edge
PIC18CXXX — 50 ns
PIC18LCXXX 100 ns
81 TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
T
CY —ns
Note 1: Requires the use of Parameter # 73A.
2: Only if Parameter # 71A and # 72A are used.