Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 247
PIC18CXX2
TABLE 21-5: PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V)
FIGURE 21-6: CLKOUT AND I/O TIMING
TABLE 21-6: CLKOUT AND I/O TIMING REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
T
RC PLL Start-up Time (Lock Time) — 2 ms
CLK CLKOUT Stability (Jitter) using PLL -2 +2 %
Param.
No.
Symbol Characteristic Min Typ Max Units Conditions
10 TosH2ckL OSC1 to CLKOUT — 75 200 ns (1)
11 TosH2ckH OSC1 to CLKOUT — 75 200 ns (1)
12 TckR CLKOUT rise time — 35 100 ns (1)
13 TckF CLKOUT fall time — 35 100 ns (1)
14 TckL2ioV CLKOUT  to Port out valid — — 0.5T
CY + 20 ns (1)
15 TioV2ckH Port in valid before CLKOUT  0.25T
CY + 25 — — ns (1)
16 TckH2ioI Port in hold after CLKOUT  0——ns(1)
17 TosH2ioV OSC1 (Q1 cycle) to Port out valid — 50 150 ns
18 TosH2ioI OSC1 (Q2 cycle) to
Port input invalid
(I/O in hold time)
PIC18CXXX 100 — — ns
18A PIC18LCXXX 200 — — ns
19 TioV2osH Port input valid to OSC1
(I/O in setup time)
0——ns
20 TioR Port output rise time PIC18CXXX — 12 25 ns
20A PIC18LCXXX — — 50 ns
21 TioF Port output fall time PIC18CXXX — 12 25 ns
21A PIC18LCXXX — — 50 ns
22†† T
INP INT pin high or low time TCY ——ns
23†† T
RBP RB7:RB4 change INT high or low time TCY ——ns
24†† T
RCP RC7:RC4 change INT high or low time 20 ns
†† These parameters are asynchronous events not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKOUT output is 4 x T
OSC.
Note: Refer to Figure 21-4 for load conditions.
OSC1
CLKOUT
I/O Pin
(input)
I/O Pin
(output)
Q4
Q1
Q2 Q3
10
13
14
17
20, 21
19
18
15
11
12
16
old value
new value