Datasheet

PIC18CXX2
DS39026D-page 210  1999-2013 Microchip Technology Inc.
IORLW Inclusive OR literal with WREG
Syntax: [ label ] IORLW k
Operands: 0  k  255
Operation: (WREG) .OR. k  WREG
Status Affected: N,Z
Encoding:
0000 1001 kkkk kkkk
Description: The contents of WREG are OR’ed
with the eight-bit literal 'k'. The
result is placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
Data
Write to
WREG
Example:
IORLW 0x35
Before Instruction
WREG = 0x9A
After Instruction
WREG = 0xBF
IORWF Inclusive OR WREG with f
Syntax: [ label ] IORWF f [,d [,a]
Operands: 0  f  255
d  [0,1]
a  [0,1]
Operation: (WREG) .OR. (f)  dest
Status Affected: N,Z
Encoding:
0001 00da ffff ffff
Description: Inclusive OR WREG with register
'f'. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is
placed back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ = 1, then the bank will be
selected as per the BSR value
(default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
Write to
destination
Example:
IORWF RESULT, 0, 1
Before Instruction
RESULT = 0x13
WREG = 0x91
After Instruction
RESULT = 0x13
WREG = 0x93