Datasheet

PIC18CXX2

DS39026D-page 108  1999-2013 Microchip Technology Inc.

13.1 CCP1 Module

Capture/Compare/PWM Register 1 (CCPR1) is com-

prised of two 8-bit registers: CCPR1L (low byte) and

CCPR1H (high byte). The CCP1CON register controls

the operation of CCP1. All are readable and writable.

TABLE 13-1: CCP MODE - TIMER

RESOURCE

13.2 CCP2 Module

Capture/Compare/PWM Register2 (CCPR2) is com-

prised of two 8-bit registers: CCPR2L (low byte) and

CCPR2H (high byte). The CCP2CON register controls

the operation of CCP2. All are readable and writable.

TABLE 13-2: INTERACTION OF TWO CCP MODULES

CCP Mode Timer Resource

Capture

Compare

PWM

Timer1 or Timer3

Timer2

CCPx Mode CCPy Mode Interaction

Capture Capture TMR1 or TMR3 time-base. Time-base can be different for each CCP.

Capture Compare The compare could be configured for the special event trigger,

which clears either TMR1, or TMR3, depending upon which time-base is used.

Compare Compare The compare(s) could be configured for the special event trigger,

which clears TMR1, or TMR3, depending upon which time-base is used.

PWM PWM The PWMs will have the same frequency and update rate (TMR2 interrupt).

PWM Capture None.

PWM Compare None.