Information
PIC18CXX2
DS80058H-page 4 2002 Microchip Technology Inc.
11. Module: I/O (PORTB
Interrupt-on-Change)
The RB Port Change Flag bit of the INTCON reg-
ister (RBIF, INTCON<0>) may be inadvertently
cleared, even when the PORTB<7:4> pins have
not been read. This will occur only when the follow-
ing two conditions occur simultaneously:
• The four Least Significant bits of the
BSR register are equal to 0Fh
(BSR<3:0> = ‘1111’), and
• Any instruction that contains 81h in its
8 Least Significant bits (i.e., register file
addresses, literal data, address offsets,
etc.) is executed.
Work around
All work arounds will involve setting the contents of
BSR<3:0> to some value other than 0Fh. In addition
to those proposed below, other solutions may exist.
1. When developing or modifying code, keep
these guidelines in mind:
• Assign 12-bit addresses to all variables.
This allows the assembler to know when
Access Banking can be used.
• Do not set the BSR to point to Bank 15
(BSR = 0Fh).
• Allow the assembler to manipulate the
Access bit present in most instructions.
Accessing the SFRs in Bank 15 will be
done through the Access Bank. Con-
tinue to use the BSR to select Banks 1
through 5, and the upper half of Bank 0.
2. If accessing a part of Bank 15 is required and
the use of Access Banking is not possible,
consider using indirect addressing.
3. If pointing the BSR to Bank 15 is unavoidable,
review the absolute file listing. Verify that no
instructions contain 81h in the 8 Least Signifi-
cant bits, while the BSR points to Bank 15
(BSR = 0Fh).
12. Module: Interrupts
When an interrupt occurs simultaneously with the
clearing of one or more interrupt enable flags in the
INTCON, PIE1 or PIE2 registers, the instruction
immediately following the interrupted instruction
may be executed before vectoring to the Interrupt
Service Routine (ISR). If that instruction is a con-
trol operation, the ISR may not execute as
intended.
In the case of conditional branch instructions, the
first instruction of the ISR may be skipped if the
tested condition would have resulted in a branch.
In the case of GOTO, CALL, or BRA instructions,
program execution may vector to the address
encoded in the instruction; the ISR will not be exe-
cuted at all. The GIE bit will still be cleared, dis-
abling all interrupts.
Additionally, on return from the interrupt (by exe-
cuting RETFIE), the instruction following the inter-
rupted instruction may be executed again.
There may be other interrupt related symptoms.
Work around
Three possible solutions are presented here.
Other solutions may exist. None of these require
special attention when setting interrupt enable bits.
1. All instructions that clear interrupt enable bits
should be followed by a NOP instruction.
2. Prior to disabling any interrupt source, disable
all interrupts by clearing the GIE bit
(INTCON<7>). After disabling the desired inter-
rupts, re-enable all interrupts by setting GIE.
3. If interrupt priority is being used:
a)clear both GIEL and GIEH (in order) bits
(INTCON<7:6>) to disable all peripheral
interrupts
b)clear the desired interrupt enable bits
c) set both GIEH and GIEL, in order to re-enable
peripheral interrupts