Information

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller SPDIP 28 8-Bit 40 MHz I/O number 22

 2002 Microchip Technology Inc. DS80058H-page 1

PIC18CXX2

The PIC18CXX2 (Rev. B) parts you have received con-

form functionally to the Device Data Sheet

(DS39026C), except for the anomalies described

below.

All the problems listed here will be addressed in future

revisions of the PIC18CXX2 silicon.

1. Module: CPU

Using the LFSR instruction to load a value into the

specified FSR register, may also corrupt a RAM

location.

Work around

Do not use the LFSR instruction. The use of MOVLW

and MOVWF instructions can be implemented to

load the FSR registers. The WREG register may

need to be saved before these operations and

restored afterwards.

EXAMPLE 1: DEFINED OPERATION

EXAMPLE 2: WORK AROUND

2. Module: CCP

When the CCP module is configured to

Compare mode toggle output pin

(CCPxCON = b’00xx0010’), unexpected pin

operation may be observed.

When the timer used for the CCP module time-

base is configured to have a prescale ratio greater

than 1:1, the output on the CCP pin will toggle the

prescaled number of times for each compare

match. That is, for a n:1 timer prescale ratio, the

CCP output pin will toggle n times at each com-

pare match. The toggle occurs each instruction

cycle (T

CY).

Work around

The prescale ratio for the timer used as the CCP

module time-base must be 1:1. If a longer com-

pare time is needed, the timer must be running in

Timer mode or Synchronized Counter mode

(external clock source).

Date Codes that pertain to this issue:

ALL

3. Module: Oscillator

In-Circuit Serial Programming

(ICSP

) may

become unpredictable when a free-running clock

source is present on OSC1.

When entering ICSP mode, the PIC18C452

switches from OSC1 to RB6 for its external clock

source. Refer to the PIC18CXXX Programming

Specification (DS39028) for additional information.

If OSC1 is high at the time, a high-to-low transition

occurs upon the transition to RB6.The ICSP logic

interprets this as a clock, and advances the inter-

nal clock logic to Q2. This causes an unrecover-

able mismatch between ICSP logic and the clock.

Work around

Before entering ICSP mode, OSC1 must be driven

to and held in a low state. This must occur before

changing states on MCLR

/VPP, RB6 and RB7.

LFSR FSR1, Pointer

;

; Optionally save the WREG register

;

MOVLW HIGH (Pointer)

MOVWF FSR1H

MOVLW LOW (Pointer)

MOVWF FSR1L

;

; Optionally restore the WREG register

;

Note: When the manufacture date of a newer

version of silicon is in production, the last

date where this issue may occur, will be

specified.

PIC18CXX2 Rev. B Silicon/Data Sheet Errata

Note: As with any windowed EPROM device, please cover the window at all times, except when erasing.

Summary of content (12 pages)

PAGE 1
M PIC18CXX2 PIC18CXX2 Rev. B Silicon/Data Sheet Errata The PIC18CXX2 (Rev. B) parts you have received conform functionally to the Device Data Sheet (DS39026C), except for the anomalies described below. All the problems listed here will be addressed in future revisions of the PIC18CXX2 silicon. 1. Module: CPU Using the LFSR instruction to load a value into the specified FSR register, may also corrupt a RAM location. Work around Do not use the LFSR instruction.
PAGE 2
PIC18CXX2 4. Module: CCP (Compare Mode) 5. Module: Timer1 and Timer3 The Compare mode may not operate as expected when configuring the compare match to drive the I/O pin low (CCPxM<3:0> = 1001). When the CCP module is changed to compare output low (CCPxM<3:0> = 1001) from any other non-compare CCP mode, the I/O pin will immediately be driven low, regardless of the state of the I/O data latch. The pin will remain low when the compare match occurs (see Table 1).
PAGE 3
PIC18CXX2 7. Module: MSSP (I2C Master Mode) The BF Status bit (SSPSTAT<0>) may be inadvertently cleared, even if the buffer has not been read. This will occur when both of the following two conditions are met: • • The four Least Significant bits of the BSR are equal to 0Fh (BSR<3:0> = '1111'), and Any instruction that contains C9h in its 8 Least Significant bits (i.e., register file address, literal data, instruction address offset, etc.) is executed.
PAGE 4
PIC18CXX2 11. Module: I/O (PORTB Interrupt-on-Change) The RB Port Change Flag bit of the INTCON register (RBIF, INTCON<0>) may be inadvertently cleared, even when the PORTB<7:4> pins have not been read. This will occur only when the following two conditions occur simultaneously: • • The four Least Significant bits of the BSR register are equal to 0Fh (BSR<3:0> = ‘1111’), and Any instruction that contains 81h in its 8 Least Significant bits (i.e.
PAGE 5
PIC18CXX2 Clarifications/Corrections to the Data Sheet: 3. Module: Timer1 In the Device Data Sheet (DS39026C), the following clarifications and corrections should be noted. Section 11.1 (Timer1 Operation) is amended with the following clarification: When Timer1 is configured to operate as an asynchronous counter, care must be taken that there is no incoming pulse while the module is being turned off.
PAGE 6
PIC18CXX2 4. Module: Electrical Specifications (HS+PLL mode), the maximum clock and oscillator frequency has been changed to 6.25 MHz. Other values of related parameters have changed accordingly. The operating frequency range for extended temperature devices has been changed. The maximum external clock frequency (EC and ECIO modes) and oscillator frequency (HS mode) for extended temperature devices has been changed to 25 MHz. When the PLL is used TABLE 21-4: EXTERNAL CLOCK TIMING REQUIREMENTS Param.
PAGE 7
PIC18CXX2 4. Module: Electrical Specifications (Continued) Figure 21-3 (below), reflecting the voltagefrequency performance of extended temperature devices, is added to the Device Data Sheet: FIGURE 21-3: PIC18CXX2 VOLTAGE-FREQUENCY GRAPH (EXTENDED) 6.0V 5.5V Voltage 5.0V PIC18CXX2-E 4.5V 4.2V 4.0V 3.5V 3.0V 2.5V 2.0V 25 MHz Frequency In addition, the title of Figure 21-1 is amended to read: “PIC18CXX2 Voltage-Frequency Graph (Industrial)”  2002 Microchip Technology Inc.
PAGE 8
PIC18CXX2 5. Module: Interrupts “It is important to note, however, that clearing the GIE/GIEH bit, regardless of the state of the IPEN bit, will disable all interrupts.” The operation of the GIE/GIEH bit (INTCON<7>) is clarified as follows: when the bit is cleared, all interrupts are disabled. This is regardless of the state of the IPEN bit (RCON<7>), the priority of the interrupt, or whether or not the interrupt is unmasked.
PAGE 9
PIC18CXX2 6. Module: USART The operation of the USART Transmit Interrupt flag bit TXIF (PIR1<4>) is clarified as follows: TXIF is not cleared immediately upon loading data into the transmit buffer TXREG. The flag bit becomes valid in the second instruction cycle following the load instruction (see Example 1). Polling TXIF immediately following a load of TXREG will give invalid results (Example 2).
PAGE 10
PIC18CXX2 REVISION HISTORY Rev H Document Under Clarifications/Corrections to the Data Sheet, added Interrupt issue for GIE/GIEH bit (page 8, item 5). Added USART issue (page 9, issue 6). Rev G Document Added Interrupt issue (page 4, item 12) Under Clarifications/Corrections to the Data Sheet, added Electrical Specifications issue for extended temperature devices (pages 6 and 7, item 4). Rev F Document Added I/O Port (PORTB - Interrupt-on-Change) issue (page 4, item 11).
PAGE 11
Note the following details of the code protection feature on PICmicro® MCUs. • • • • • • The PICmicro family meets the specifications contained in the Microchip Data Sheet. Microchip believes that its family of PICmicro microcontrollers is one of the most secure products of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 12
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