Datasheet

PIC18CXX2
DS39026D-page 204 1999-2013 Microchip Technology Inc.
COMF Complement f
Syntax: [ label ] COMF f [,d [,a]
Operands: 0 f 255
d [0,1]
a [0,1]
Operation: dest
Status Affected: N,Z
Encoding:
0001 11da ffff ffff
Description: The contents of register 'f' are com-
plemented. If 'd' is 0, the result is
stored in WREG. If 'd' is 1, the
result is stored back in register 'f'
(default). If ‘a’ is 0, the Access
Bank will be selected, overriding
the BSR value. If ‘a’ = 1, then the
bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
Write to
destination
Example:
COMF REG, 0, 0
Before Instruction
REG = 0x13
After Instruction
REG = 0x13
WREG = 0xEC
(f)
CPFSEQ
Compare f with WREG,
skip if f = WREG
Syntax: [ label ] CPFSEQ f [,a]
Operands: 0 f 255
a [0,1]
Operation: (f) – (WREG),
skip if (f) = (WREG)
(unsigned comparison)
Status Affected: None
Encoding:
0110 001a ffff ffff
Description: Compares the contents of data
memory location 'f' to the contents
of WREG by performing an
unsigned subtraction.
If 'f' = WREG
, then the fetched
instruction is discarded and a NOP
is executed instead, making this a
two-cycle instruction. If ‘a’ is 0, the
Access Bank will be selected, over-
riding the BSR value. If ‘a’ = 1, then
the bank will be selected as per the
BSR value (default).
Words: 1
Cycles: 1(2)
Note: 3 cycles if skip and followed
by a 2-word instruction.
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
If skip and followed by 2-word instruction:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
No
operation
Example:
HERE CPFSEQ REG, 0
NEQUAL :
EQUAL :
Before Instruction
PC Address = HERE
WREG = ?
REG = ?
After Instruction
If REG = WREG;
PC = Address (EQUAL)
If REG  WREG;
PC = Address (NEQUAL)