Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 193
PIC18CXX2
19.1 Instruction Set
ADDLW ADD literal to WREG
Syntax: [ label ] ADDLW k
Operands: 0  k  255
Operation: (WREG) + k  WREG
Status Affected: N,OV, C, DC, Z
Encoding:
0000 1111 kkkk kkkk
Description: The contents of WREG are added
to the 8-bit literal 'k' and the result is
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
Data
Write to
WREG
Example:
ADDLW 0x15
Before Instruction
WREG = 0x10
After Instruction
WREG = 0x25
ADDWF ADD WREG to f
Syntax: [ label ] ADDWF f [,d [,a] f [,d [,a]
Operands: 0  f  255
d  [0,1]
a  [0,1]
Operation: (WREG) + (f)  dest
Status Affected: N,OV, C, DC, Z
Encoding:
0010 01da ffff ffff
Description: Add WREG to register 'f'. If 'd' is 0,
the result is stored in WREG. If 'd'
is 1, the result is stored back in reg-
ister 'f' (default). If ‘a’ is 0, the
Access Bank will be selected. If ‘a’
is 1, the BSR is used.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
Write to
destination
Example:
ADDWF REG, 0, 0
Before Instruction
WREG = 0x17
REG = 0xC2
After Instruction
WREG = 0xD9
REG = 0xC2