Datasheet

 1999-2013 Microchip Technology Inc. DS39026D-page 179
PIC18CXX2
18.0 SPECIAL FEATURES OF THE
CPU
There are several features intended to maximize sys-
tem reliability, minimize cost through elimination of
external components, provide power saving operating
modes and offer code protection. These are:
• OSC Selection
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-circuit Serial Programming
All PIC18CXX2 devices have a Watchdog Timer, which
is permanently enabled via the configuration bits or
software-controlled. It runs off its own RC oscillator for
added reliability. There are two timers that offer neces-
sary delays on power-up. One is the Oscillator Start-up
Timer (OST), intended to keep the chip in RESET until
the crystal oscillator is stable. The other is the Power-
up Timer (PWRT), which provides a fixed delay on
power-up only, designed to keep the part in RESET
while the power supply stabilizes. With these two tim-
ers on-chip, most applications need no external
RESET circuitry.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up or through an interrupt. Several oscillator
options are also made available to allow the part to fit
the application. The RC oscillator option saves system
cost, while the LP crystal option saves power. A set of
configuration bits are used to select various options.
18.1 Configuration Bits
The configuration bits can be programmed (read as '0'),
or left unprogrammed (read as '1'), to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h - 3FFFFFh),
which can only be accessed using table reads and
table writes.
TABLE 18-1: CONFIGURATION BITS AND DEVICE IDS
File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Default/
Unprogrammed
Value
300000h CONFIG1L CP CP CP CP CP CP CP CP 1111 1111
300001h CONFIG1H
— — OSCSEN — — FOSC2 FOSC1 FOSC0 111- -111
300002h CONFIG2L
— — — — BORV1 BORV0 BODEN PWRTEN ---- 1111
300003h CONFIG2H
— — — — WDTPS2 WDTPS1 WDTPS0 WDTEN ---- 1111
300005h CONFIG3H
— — — — — — — CCP2MX ---- ---1
300006h CONFIG4L
— — — — — — LVEN STVREN ---- --11
3FFFFEh DEVID1 DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 0000 0000
3FFFFFh DEVID2 DEV10 DEV9 DEV8 DEV7 DEV6 DEV5 DEV4 DEV3 0000 0010
Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition.
Shaded cells are unimplemented, read as ‘0’