Datasheet

PIC17C7XX
DS30289C-page 86  1998-2013 Microchip Technology Inc.
10.7 PORTG and DDRG Registers
PORTG is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is DDRG. A '1' in
DDRG configures the corresponding port pin as an
input. A '0' in the DDRG register configures the corre-
sponding port pin as an output. Reading PORTG reads
the status of the pins, whereas writing to PORTG will
write to the port latch.
The lower four bits of PORTG are multiplexed with four
channels of the 10-bit A/D converter.
The remaining bits of PORTG are multiplexed with
peripheral output and inputs. RG4 is multiplexed with
the CAP3 input, RG5 is multiplexed with the PWM3
output, RG6 and RG7 are multiplexed with the
USART2 functions.
Upon RESET, RG3:RG0 is automatically configured as
analog inputs and must be configured in software to be
a digital I/O.
Example 10-7 shows the instruction sequence to initial-
ize PORTG. The Bank Select Register (BSR) must be
selected to Bank 5 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-7: INITIALIZING PORTG
FIGURE 10-14: BLOCK DIAGRAM OF RG3:RG0
MOVLB 5 ; Select Bank 5
MOVLW 0x0E ; Configure PORTG as
MOVPF WREG, ADCON1 ; digital
CLRF PORTG, F ; Initialize PORTG data
; latches before
; the data direction
; register
MOVLW 0x03 ; Value used to init
; data direction
MOVWF DDRG ; Set RG<1:0> as inputs
; RG<7:2> as outputs
Data Bus
WR PORTG
WR DDRG
RD PORTG
Data Latch
DDRG Latch
P
V
SS
I/O pin
PCFG3:PCFG0
Q
D
QCK
Q
D
QCK
EN
QD
EN
N
ST
Input
Buffer
VDD
RD DDRG
To other pads
VAIN
CHS3:CHS0
To other pads
Note: I/O pins have protection diodes to VDD and VSS.