Datasheet

PIC17C7XX
DS30289C-page 82  1998-2013 Microchip Technology Inc.
10.5 PORTE and DDRE Register
PORTE is a 4-bit bi-directional port. The corresponding
data direction register is DDRE. A '1' in DDRE config-
ures the corresponding port pin as an input. A '0' in the
DDRE register configures the corresponding port pin
as an output. Reading PORTE reads the status of the
pins, whereas writing to PORTE will write to the port
latch. PORTE is multiplexed with the system bus.
When operating as the system bus, PORTE contains
the control signals for the address/data bus
(AD15:AD0). These control signals are Address Latch
Enable (ALE), Output Enable (OE
) and Write (WR).
The control signals OE
and WR are active low signals.
The timing for the system bus is shown in the Electrical
Specifications section.
Example 10-5 shows an instruction sequence to initial-
ize PORTE. The Bank Select Register (BSR) must be
selected to Bank 1 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-5: INITIALIZING PORTE
FIGURE 10-11: BLOCK DIAGRAM OF RE2:RE0 (IN I/O PORT MODE)
Note: Three pins of this port are configured as
the system bus when the device’s configu-
ration bits are selected to Microprocessor
or Extended Microcontroller modes. The
other pin is a general purpose I/O or
Capture4 pin. In the two other micro-
controller modes, RE2:RE0 are general
purpose I/O pins.
MOVLB 1 ; Select Bank 1
CLRF PORTE, F ; Initialize PORTE data
; latches before setting
; the data direction
; register
MOVLW 0x03 ; Value used to initialize
; data direction
MOVWF DDRE ; Set RE<1:0> as inputs
; RE<3:2> as outputs
; RE<7:4> are always
; read as '0'
Note: I/O pins have protection diodes to VDD and VSS.
Q
D
CK
TTL
0
1
Q
D
CK
R
S
Input
Buffer
Port
Data
Data Bus
RD_PORTE
WR_PORTE
RD_DDRE
WR_DDRE
EX_EN
CNTL
DRV_SYS
System Bus
Control