Datasheet

PIC17C7XX
DS30289C-page 72  1998-2013 Microchip Technology Inc.
10.1 PORTA Register
PORTA is a 6-bit wide latch. PORTA does not have a
corresponding Data Direction Register (DDR). Upon a
device RESET, the PORTA pins are forced to be hi-
impedance inputs. For the RA4 and RA5 pins, the
peripheral module controls the output. When a device
RESET occurs, the peripheral module is disabled, so
these pins are forced to be hi-impedance inputs.
Reading PORTA reads the status of the pins.
The RA0 pin is multiplexed with the external interrupt,
INT. The RA1 pin is multiplexed with TMR0 clock input,
RA2 and RA3 are multiplexed with the SSP functions,
and RA4 and RA5 are multiplexed with the USART1
functions. The control of RA2, RA3, RA4 and RA5 as
outputs, is automatically configured by their multi-
plexed peripheral module when the module is enabled.
10.1.1 USING RA2, RA3 AS OUTPUTS
The RA2 and RA3 pins are open drain outputs. To use
the RA2 and/or the RA3 pin(s) as output(s), simply
write to the PORTA register the desired value. A '0' will
cause the pin to drive low, while a '1' will cause the pin
to float (hi-impedance). An external pull-up resistor
should be used to pull the pin high. Writes to the RA2
and RA3 pins will not affect the other PORTA pins.
Example 10-1 shows an instruction sequence to initial-
ize PORTA. The Bank Select Register (BSR) must be
selected to Bank 0 for the port to be initialized. The fol-
lowing example uses the MOVLB instruction to load the
BSR register for bank selection.
EXAMPLE 10-1: INITIALIZING PORTA
FIGURE 10-1: RA0 AND RA1 BLOCK
DIAGRAM
FIGURE 10-2: RA2 BLOCK DIAGRAM
Note: When using the RA2 or RA3 pin(s) as out-
put(s), read-modify-write instructions (such
as BCF, BSF, BTG) on PORTA are not
recommended.
Such operations read the port pins, do the
desired operation, and then write this value
to the data latch. This may inadvertently
cause the RA2 or RA3 pins to switch from
input to output (or vice-versa).
To avoid this possibility, use a shadow reg-
ister for PORTA. Do the bit operations on
this shadow register and then move it to
PORTA.
MOVLB 0 ; Select Bank 0
MOVLW 0xF3 ;
MOVWF PORTA ; Initialize PORTA
; RA<3:2> are output low
; RA<5:4> and RA<1:0>
; are inputs
; (outputs floating)
Note: Input pins have protection diodes to VDD and VSS.
Data Bus
RD_PORTA
(Q2)
Note: I/O pin has protection diodes to VSS.
Data Bus
WR_PORTA
(Q4)
QD
Q
CK
RD_PORTA
(Q2)
QD
EN
Peripheral Data In
1
0
I
2
C Mode Enable
SCL
Out