Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 69
PIC17C7XX
Example 9-4 shows the sequence to do a 16 x 16
signed multiply. Equation 9-2 shows the algorithm
used. The 32-bit result is stored in four registers,
RES3:RES0. To account for the sign bits of the argu-
ments, each argument pairs most significant bit (MSb)
is tested and the appropriate subtractions are done.
EQUATION 9-2: 16 x 16 SIGNED
MULTIPLICATION
ALGORITHM
EXAMPLE 9-4: 16 x 16 SIGNED
MULTIPLY ROUTINE
RES3:RES0
= ARG1H:ARG1L  ARG2H:ARG2L
= (ARG1H  ARG2H  2
16
)+
(ARG1H  ARG2L  2
8
)+
(ARG1L  ARG2H  2
8
)+
(ARG1L  ARG2L) +
(-1  ARG2H<7>  ARG1H:ARG1L  2
16
)+
(-1  ARG1H<7>  ARG2H:ARG2L  2
16
)
MOVFP ARG1L, WREG
MULWF ARG2L ; ARG1L * ARG2L ->
; PRODH:PRODL
MOVPF PRODH, RES1 ;
MOVPF PRODL, RES0 ;
;
MOVFP ARG1H, WREG
MULWF ARG2H ; ARG1H * ARG2H ->
; PRODH:PRODL
MOVPF PRODH, RES3 ;
MOVPF PRODL, RES2 ;
;
MOVFP ARG1L, WREG
MULWF ARG2H ; ARG1L * ARG2H ->
; PRODH:PRODL
MOVFP PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFP PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
MOVFP ARG1H, WREG ;
MULWF ARG2L ; ARG1H * ARG2L ->
; PRODH:PRODL
MOVFP PRODL, WREG ;
ADDWF RES1, F ; Add cross
MOVFP PRODH, WREG ; products
ADDWFC RES2, F ;
CLRF WREG, F ;
ADDWFC RES3, F ;
;
BTFSS ARG2H, 7 ; ARG2H:ARG2L neg?
GOTO SIGN_ARG1 ; no, check ARG1
MOVFP ARG1L, WREG ;
SUBWF RES2 ;
MOVFP ARG1H, WREG ;
SUBWFB RES3
;
SIGN_ARG1
BTFSS ARG1H, 7 ; ARG1H:ARG1L neg?
GOTO CONT_CODE ; no, done
MOVFP ARG2L, WREG ;
SUBWF RES2 ;
MOVFP ARG2H, WREG ;
SUBWFB RES3
;
CONT_CODE
: