Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 47
PIC17C7XX
FIGURE 7-5: PIC17C7XX REGISTER FILE MAP
Addr Unbanked
00h
INDF0
01h
FSR0
02h
PCL
03h
PCLATH
04h
ALUSTA
05h
T0STA
06h
CPUSTA
07h
INTSTA
08h
INDF1
09h
FSR1
0Ah
WREG
0Bh
TMR0L
0Ch
TMR0H
0Dh
TBLPTRL
0Eh
TBLPTRH
0Fh
BSR
Bank 0 Bank 1
(1)
Bank 2
(1)
Bank 3
(1)
Bank 4
(1)
Bank 5
(1)
Bank 6
(1)
Bank 7
(1)
Bank 8
(1,4)
10h
PORTA DDRC TMR1 PW1DCL PIR2 DDRF SSPADD PW3DCL DDRH
11h
DDRB PORTC TMR2 PW2DCL PIE2 PORTF SSPCON1 PW3DCH PORTH
12h
PORTB DDRD TMR3L PW1DCH
—
DDRG SSPCON2 CA3L DDRJ
13h
RCSTA1 PORTD TMR3H PW2DCH RCSTA2 PORTG SSPSTAT CA3H PORTJ
14h
RCREG1 DDRE PR1 CA2L RCREG2 ADCON0 SSPBUF CA4L
—
15h
TXSTA1 PORTE PR2 CA2H TXSTA2 ADCON1
—
CA4H
—
16h
TXREG1 PIR1 PR3L/CA1L TCON1 TXREG2 ADRESL
—
TCON3
—
17h
SPBRG1 PIE1 PR3H/CA1H TCON2 SPBRG2 ADRESH
— — —
Unbanked
18h
PRODL
19h
PRODH
1Ah
1Fh
General
Purpose
RAM
Bank 0
(2)
Bank 1
(2)
Bank 2
(2)
Bank 3
(2,3)
20h
FFh
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
General
Purpose
RAM
Note 1: SFR file locations 10h - 17h are banked. The lower nibble of the BSR specifies the bank. All unbanked
SFRs ignore the Bank Select Register (BSR) bits.
2: General Purpose Registers (GPR) locations 20h - FFh, 120h - 1FFh, 220h - 2FFh, and 320h - 3FFh are
banked. The upper nibble of the BSR specifies this bank. All other GPRs ignore the Bank Select Register
(BSR) bits.
3: RAM bank 3 is not implemented on the PIC17C752 and the PIC17C762. Reading any unimplemented reg-
ister reads ‘0’s.
4: Bank 8 is only implemented on the PIC17C76X devices.