Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 35
PIC17C7XX
6.2 Peripheral Interrupt Enable
Register1 (PIE1) and Register2
(PIE2)
These registers contains the individual enable bits for
the peripheral interrupts.
REGISTER 6-2: PIE1 REGISTER (ADDRESS: 17h, BANK 1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE
bit 7 bit 0
bit 7 RBIE: PORTB Interrupt-on-Change Enable bit
1 = Enable PORTB interrupt-on-change
0 = Disable PORTB interrupt-on-change
bit 6 TMR3IE: TMR3 Interrupt Enable bit
1 = Enable TMR3 interrupt
0 = Disable TMR3 interrupt
bit 5 TMR2IE: TMR2 Interrupt Enable bit
1 = Enable TMR2 interrupt
0 = Disable TMR2 interrupt
bit 4 TMR1IE: TMR1 Interrupt Enable bit
1 = Enable TMR1 interrupt
0 = Disable TMR1 interrupt
bit 3 CA2IE: Capture2 Interrupt Enable bit
1 = Enable Capture2 interrupt
0 = Disable Capture2 interrupt
bit 2 CA1IE: Capture1 Interrupt Enable bit
1 = Enable Capture1 interrupt
0 = Disable Capture1 interrupt
bit 1 TX1IE: USART1 Transmit Interrupt Enable bit
1 = Enable USART1 Transmit buffer empty interrupt
0 = Disable USART1 Transmit buffer empty interrupt
bit 0 RC1IE: USART1 Receive Interrupt Enable bit
1 = Enable USART1 Receive buffer full interrupt
0 = Disable USART1 Receive buffer full interrupt
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown