Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 291
PIC17C7XX
F
Family of Devices
PIC17C75X ................................................................... 8
FERR ................................................................................ 125
Flowcharts
Acknowledge............................................................. 166
Master Receiver........................................................ 163
Master Transmit........................................................ 160
RESTART Condition................................................. 157
Start Condition .......................................................... 155
STOP Condition ........................................................ 168
FOSC0 .............................................................................. 191
FOSC1 .............................................................................. 191
FS0 ..................................................................................... 51
FS1 ..................................................................................... 51
FS2 ..................................................................................... 51
FS3 ..................................................................................... 51
FSR0................................................................................... 54
FSR1................................................................................... 54
G
GCE .................................................................................. 136
General Call Address Sequence....................................... 149
General Call Address Support .......................................... 149
General Call Enable bit, GCE ........................................... 136
General Format for Instructions ........................................ 198
General Purpose RAM........................................................ 43
General Purpose RAM Bank............................................... 57
General Purpose Register (GPR) ....................................... 46
GLINTD......................................................... 39, 52, 111, 194
Global Interrupt Disable bit, GLINTD .................................. 39
GOTO ............................................................................... 212
GPR (General Purpose Register) ....................................... 46
GPR Banks ......................................................................... 57
Graphs
RC Oscillator Frequency vs. V
DD (CEXT = 100 pF)... 268
RC Oscillator Frequency vs. V
DD (CEXT = 22 pF)..... 268
RC Oscillator Frequency vs. V
DD (CEXT = 300 pF)... 269
Transconductance of LF Oscillator vs.V
DD ............... 270
Transconductance of XT Oscillator vs. V
DD.............. 270
Typical RC Oscillator vs. Temperature ..................... 267
H
Hardware Multiplier ............................................................. 67
I
I/O Ports
Bi-directional ............................................................... 93
I/O Ports...................................................................... 71
Programming Considerations ..................................... 93
Read-Modify-Write Instructions................................... 93
Successive Operations ............................................... 94
I
2
C..................................................................................... 143
I2C Input ........................................................................... 279
I
2
C Master Mode Receiver Flow Chart ............................. 163
I
2
C Master Mode Reception.............................................. 162
I
2
C Master Mode RESTART Condition............................. 156
I
2
C Mode Selection ........................................................... 143
I
2
C Module
Acknowledge Flow Chart .......................................... 166
Acknowledge Sequence Timing................................ 165
Addressing................................................................ 145
Baud Rate Generator................................................ 153
Block Diagram........................................................... 151
BRG Block Diagram.................................................. 153
BRG Reset due to SDA Collision.............................. 172
BRG Timing .............................................................. 153
Bus Arbitration .......................................................... 170
Bus Collision............................................................. 170
Acknowledge .................................................... 170
RESTART Condition......................................... 173
RESTART Condition Timing (Case1)............... 173
RESTART Condition Timing (Case2)............... 173
START Condition.............................................. 171
START Condition Timing.......................... 171, 172
STOP Condition................................................ 174
STOP Condition Timing (Case1) ...................... 174
STOP Condition Timing (Case2) ...................... 174
Transmit Timing................................................ 170
Bus Collision Timing ................................................. 170
Clock Arbitration ....................................................... 169
Clock Arbitration Timing (Master Transmit) .............. 169
Conditions to not give ACK
Pulse............................. 144
General Call Address Support.................................. 149
Master Mode............................................................. 151
Master Mode 7-bit Reception timing......................... 164
Master Mode Operation............................................ 152
Master Mode Start Condition.................................... 154
Master Mode Transmission ...................................... 159
Master Mode Transmit Sequence ............................ 152
Master Transmit Flowchart ....................................... 160
Multi-Master Communication.................................... 170
Multi-master Mode.................................................... 152
Operation.................................................................. 143
Repeat Start Condition timing................................... 156
RESTART Condition Flowchart ................................ 157
Slave Mode............................................................... 144
Slave Reception ....................................................... 145
Slave Transmission .................................................. 146
SSPBUF ................................................................... 144
Start Condition Flowchart ......................................... 155
Stop Condition Flowchart ......................................... 168
Stop Condition Receive or Transmit timing .............. 167
Stop Condition timing ............................................... 167
Waveforms for 7-bit Reception ................................. 146
Waveforms for 7-bit Transmission............................ 146
I
2
C Module Address Register, SSPADD .......................... 144
I
2
C Slave Mode ................................................................ 144
INCF ................................................................................. 213
INCFSNZ .......................................................................... 214
INCFSZ............................................................................. 213
In-Circuit Serial Programming........................................... 196
INDF0 ................................................................................. 54
INDF1 ................................................................................. 54
Indirect Addressing
Indirect Addressing..................................................... 54
Operation.................................................................... 55
Registers .................................................................... 54
Initializing PORTB............................................................... 75
Initializing PORTC .............................................................. 78
Initializing PORTD .............................................................. 80
Initializing PORTE................................................... 82, 84, 86
INSTA ................................................................................. 48
Instruction Flow/Pipelining.................................................. 21
Instruction Set
ADDLW..................................................................... 202
ADDWF .................................................................... 202
ADDWFC.................................................................. 203
ANDLW..................................................................... 203
ANDWF .................................................................... 204
BCF .......................................................................... 204
BSF........................................................................... 205
BTFSC...................................................................... 205
BTFSS ...................................................................... 206