Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 29
PIC17C7XX
Bank 4
PIR2 10h 000- 0010 000- 0010
uuu- uuuu
(1)
PIE2 11h 000- 0000 000- 0000 uuu- uuuu
Unimplemented
12h ---- ---- ---- ---- ---- ----
RCSTA2 13h 0000 -00x 0000 -00u uuuu -uuu
RCREG2 14h xxxx xxxx uuuu uuuu uuuu uuuu
TXSTA2 15h 0000 --1x 0000 --1u uuuu --uu
TXREG2 16h xxxx xxxx uuuu uuuu uuuu uuuu
SPBRG2 17h 0000 0000 0000 0000 uuuu uuuu
Bank 5
DDRF 10h 1111 1111 1111 1111 uuuu uuuu
PORTF
(4)
11h 0000 0000 0000 0000 uuuu uuuu
DDRG 12h 1111 1111 1111 1111 uuuu uuuu
PORTG
(4)
13h xxxx 0000 uuuu 0000 uuuu uuuu
ADCON0 14h 0000 -0-0 0000 -0-0 uuuu uuuu
ADCON1 15h 000- 0000 000- 0000 uuuu uuuu
ADRESL 16h xxxx xxxx uuuu uuuu uuuu uuuu
ADRESH 17h xxxx xxxx uuuu uuuu uuuu uuuu
Bank 6
SSPADD 10h 0000 0000 0000 0000 uuuu uuuu
SSPCON1 11h 0000 0000 0000 0000 uuuu uuuu
SSPCON2 12h 0000 0000 0000 0000 uuuu uuuu
SSPSTAT 13h 0000 0000 0000 0000 uuuu uuuu
SSPBUF 14h xxxx xxxx uuuu uuuu uuuu uuuu
Unimplemented
15h ---- ---- ---- ---- ---- ----
Unimplemented
16h ---- ---- ---- ---- ---- ----
Unimplemented
17h ---- ---- ---- ---- ---- ----
TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED)
Register Address
Power-on Reset
Brown-out Reset
MCLR
Reset
WDT Reset
Wake-up from SLEEP
through Interrupt
Legend: u = unchanged,
x = unknown, - = unimplemented, read as '0', q = value depends on condition
Note 1: One or more bits in INTSTA, PIR1, PIR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GLINTD bit is cleared, the PC is loaded with the interrupt
vector.
3: See Table 5-3 for RESET value of specific condition.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this
port does not rely on these registers.
6: On any device RESET, these pins are configured as inputs.