Datasheet

PIC17C7XX
DS30289C-page 264  1998-2013 Microchip Technology Inc.
FIGURE 20-23: A/D CONVERSION TIMING
TABLE 20-19: A/D CONVERSION REQUIREMENTS
Param.
No.
Sym Characteristic Min Typ† Max Units Conditions
130 T
AD A/D clock period PIC17CXXX 1.6 — — sTOSC based, VREF  3.0V
PIC17LCXXX 3.0 — — sT
OSC based, VREF full range
PIC17CXXX 2.0 4.0 6.0 s A/D RC mode
PIC17LCXXX 3.0 6.0 9.0 s A/D RC mode
131 T
CNV Conversion time
(not including acquisition time) (Note 1)
11 — 12 Tad
132 T
ACQ Acquisition time (Note 2)
10
20
—
—
—
s
s The minimum time is the
amplifier settling time. This
may be used if the “new”
input voltage has not
changed by more than 1LSb
(i.e., 5 mV @ 5.12V) from
the last sampled voltage (as
stated on C
HOLD).
134 T
GO Q4 to ADCLK start — Tosc/2 — — If the A/D clock source is
selected as RC, a time of
T
CY is added before the A/D
clock starts. This allows the
SLEEP instruction to be
executed.
† Data in “Typ” column is at 5V, 25C unless otherwise stated.
Note 1: ADRES register may be read on the following T
CY cycle.
2: See Section 16.1 for minimum conditions when input voltage has changed more than 1 LSb.
131
130
132
BSF ADCON0, GO
Q4
A/D CLK
A/D DATA
ADRES
ADIF
GO
SAMPLE
OLD_DATA
SAMPLING STOPPED
DONE
NEW_DATA
(T
OSC/2)
(1)
987 210
Note 1: If the A/D clock source is selected as RC, a time of T
CY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
1 TCY
. . .
. . .