Datasheet

PIC17C7XX
DS30289C-page 260  1998-2013 Microchip Technology Inc.
FIGURE 20-19: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 20-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
110 Tbuf Bus free time 100 kHz mode 4.7 — ms Time the bus must be free
before a new transmission
can start
400 kHz mode 1.3 — ms
1 MHz mode
(1)
0.5 — ms
D102 Cb Bus capacitive loading — 400 pF
Param
No.
Sym Characteristic Min Max Units Conditions
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.
2: A fast mode (400 KHz) I
2
C bus device can be used in a standard mode I
2
C bus system, but the parameter # 107  250 ns
must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line.
Parameter #102 + #107 = 1000 + 250 = 1250 ns (for 100 kHz mode) before the SCL line is released.
3: C
b
is specified to be from 10-400pF. The minimum specifications are characterized with C
b
=10pF. The rise time spec (t
r
)
is characterized with R
p
=R
p
min. The minimum fall time specification (t
f
) is characterized with C
b
=10pF,and R
p
=R
p
max.
These are only valid for fast mode operation (V
DD=4.5-5.5V) and where the SPM bit (SSPSTAT<7>) =1.)
4: Max specifications for these parameters are valid for falling edge only. Specs are characterized with R
p
=R
p
min and
C
b
=400pF for standard mode, 200pF for fast mode, and 10pF for 1MHz mode.
121
121
120
122
TX/CK
RX/DT
pin
pin
Param
No.
Sym Characteristic Min Typ† Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock high to data out valid PIC17CXXX — — 50 ns
PIC17LCXXX — — 75 ns
121 TckRF Clock out rise time and fall time
(Master mode)
PIC17CXXX — — 25 ns
PIC17LCXXX — — 40 ns
122 TdtRF Data out rise time and fall time PIC17CXXX — — 25 ns
PIC17LCXXX — — 40 ns
† Data in “Typ” column is at 5V, 25C unless otherwise stated.