Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 255
PIC17C7XX
FIGURE 20-14: SPI MASTER MODE TIMING (CKE = 1)
TABLE 20-9: SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
SS
SCK
(CKP = 0)
SCK
(CKP = 1)
SDO
SDI
81
71 72
74
75, 76
78
80
MSb
79
73
MSb IN
BIT6 - - - - - -1
LSb IN
BIT6 - - - -1
LSb
Note: Refer to Figure 20-5 for load conditions.
Param.
No.
Symbol Characteristic Min Typ† Max Units Conditions
71 TscH SCK input high time
(Slave mode)
Continuous 1.25T
CY + 30 — — ns
71A Single Byte 40 — — ns (Note 1)
72 TscL SCK input low time
(Slave mode)
Continuous 1.25 T
CY + 30 — — ns
72A Single Byte 40 — — ns (Note 1)
73 TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge 100 — — ns
73A T
B2B Last clock edge of Byte1 to the 1st clock edge
of Byte2
1.5TCY + 40 — — ns (Note 1)
74 TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge 100 — — ns
75 TdoR SDO data output rise time — 10 25 ns
76 TdoF SDO data output fall time — 10 25 ns
78 TscR SCK output rise time (Master mode) — 10 25 ns
79 TscF SCK output fall time (Master mode) — 10 25 ns
80 TscH2doV,
TscL2doV
SDO data output valid after SCK edge — — 50 ns
81 TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge Tcy — — ns
† Data in "Typ" column is at 5V, 25°C unless otherwise stated.
Note 1: Specification 73A is only required if specifications 71A and 72A are used.