Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 23
PIC17C7XX
5.0 RESET
The PIC17CXXX differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• Brown-out Reset
•MCLR
Reset
•WDT Reset
Some registers are not affected in any RESET condi-
tion, their status is unknown on POR and unchanged in
any other RESET. Most other registers are forced to a
“RESET state”. The TO
and PD bits are set or cleared
differently in different RESET situations, as indicated in
Table 5-3. These bits, in conjunction with the POR
and
BOR
bits, are used in software to determine the nature
of the RESET. See Table 5-4 for a full description of the
RESET states of all registers.
When the device enters the “RESET state”, the Data
Direction registers (DDR) are forced set, which will
make the I/O hi-impedance inputs. The RESET state of
some peripheral modules may force the I/O to other
operations, such as analog inputs or the system bus.
A simplified block diagram of the On-Chip Reset Circuit
is shown in Figure 5-1.
FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
Note: While the device is in a RESET state, the
internal phase clock is held in the Q1 state.
Any processor mode that allows external
execution will force the RE0/ALE pin as a
low output and the RE1/OE and RE2/WR
pins as high outputs.
S
R
Q
External
Reset
MCLR
VDD
OSC1
WDT
Module
V
DD Rise
Detect
OST/PWRT
On-chip
RC OSC†
WDT
Time_Out
Power_On_Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
(Enable the PWRT timer
only during POR or BOR)
(If PWRT is invoked, or a Wake-up from
SLEEP and OSC type is XT or LF)
Reset
Enable OST
Enable PWRT
† This RC oscillator is shared with the WDT when not in a power-up sequence.
BOR
Module
Brown-out
Reset