Datasheet

PIC17C7XX
DS30289C-page 210  1998-2013 Microchip Technology Inc.
CPFSLT
Compare f with WREG,
skip if f < WREG
Syntax: [ label ] CPFSLT f
Operands: 0  f  255
Operation: (f) –WREG),
skip if (f) < (WREG)
(unsigned comparison)
Status Affected: None
Encoding:
0011 0000 ffff ffff
Description:
Compares the contents of data memory
location 'f' to the contents of WREG by
performing an unsigned subtraction.
If the contents of 'f' are less than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
Words: 1
Cycles: 1 (2)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
No
operation
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example:
HERE CPFSLT REG
NLESS :
LESS :
Before Instruction
PC = Address (HERE)
W= ?
After Instruction
If REG < WREG;
PC = Address (LESS)
If REG  WREG;
PC = Address (NLESS)
DAW Decimal Adjust WREG Register
Syntax: [label] DAW f,s
Operands: 0  f  255
s  [0,1]
Operation:
If [ [WREG<7:4> > 9].OR.[C = 1] ].AND.
[WREG<3:0> > 9]
then
WREG<7:4> + 7 f<7:4>, s<7:4>;
If [WREG<7:4> > 9].OR.[C = 1]
then
WREG<7:4> + 6 f<7:4>, s<7:4>;
else
WREG<7:4> f<7:4>, s<7:4>;
If [WREG<3:0> > 9].OR.[DC = 1]
then
WREG<3:0> + 6 f<3:0>, s<3:0>;
else
WREG<3:0> f<3:0>, s<3:0>
Status Affected: C
Encoding:
0010 111s ffff ffff
Description:
DAW adjusts the eight-bit value in
WREG, resulting from the earlier addi-
tion of two variables (each in packed
BCD format) and produces a correct
packed BCD result.
s = 0: Result is placed in Data
memory location 'f' and
WREG.
s = 1: Result is placed in Data
memory location 'f'.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
Write
register 'f'
and other
specified
register
Example:
DAW REG1, 0
Before Instruction
WREG = 0xA5
REG1 = ??
C=0
DC = 0
After Instruction
WREG = 0x05
REG1 = 0x05
C=1
DC = 0