Datasheet

PIC17C7XX
DS30289C-page 196  1998-2013 Microchip Technology Inc.
17.6 In-Circuit Serial Programming
The PIC17C7XX group of the high-end family
(PIC17CXXX) has an added feature that allows serial
programming while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage. This allows customers to manufacture boards
with unprogrammed devices and then program the
microcontroller just before shipping the product. This
also allows the most recent firmware, or a custom firm-
ware to be programmed.
Devices may be serialized to make the product unique;
“special” variants of the product may be offered and
code updates are possible. This allows for increased
design flexibility.
To place the device into the Serial Programming Test
mode, two pins will need to be placed at V
IHH. These
are the TEST pin and the MCLR
/VPP pin. Also, a
sequence of events must occur as follows:
1. The TEST pin is placed at VIHH.
2. The MCLR
/VPP pin is placed at VIHH.
There is a setup time between step 1 and step 2 that
must be met.
After this sequence, the Program Counter is pointing to
program memory address 0xFF60. This location is in
the Boot ROM. The code initializes the USART/SCI so
that it can receive commands. For this, the device must
be clocked. The device clock source in this mode is the
RA1/T0CKI pin. After delaying to allow the USART/SCI
to initialize, commands can be received. The flow is
shown in these 3 steps:
1. The device clock source starts.
2. Wait 80 device clocks for Boot ROM code to
configure the USART/SCI.
3. Commands may now be sent.
For complete details of serial programming, please
refer to the PIC17C7XX Programming Specification.
(Contact your local Microchip Technology Sales Office
for availability.)
FIGURE 17-3: TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
TABLE 17-3: ICSP INTERFACE PINS
External
Connector
Signals
To Normal
Connections
To Normal
Connections
PIC17C7XX
V
DD
VSS
MCLR/VPP
RA1/T0CKI
RA4/RX1/DT1
+5V
0V
V
PP
Dev. CLK
Data I/O
VDD
RA5/TX1/CK1Data CLK
TEST
TEST CNTL
During Programming
Name Function Type Description
RA4/RX1/DT1 DT I/O Serial Data
RA5/TX1/CK1 CK I Serial Clock
RA1/T0CKI OSCI I Device Clock Source
TEST TEST I Test mode selection control input, force to V
IHH
MCLR/VPP MCLR/VPP P Master Clear Reset and Device Programming Voltage
V
DD VDD P Positive supply for logic and I/O pins
V
SS VSS P Ground reference for logic and I/O pins