Datasheet

PIC17C7XX
DS30289C-page 186  1998-2013 Microchip Technology Inc.
16.3 Configuring Analog Port Pins
The ADCON1, and DDR registers control the operation
of the A/D port pins. The port pins that are desired as
analog inputs must have their corresponding DDR bits
set (input). If the DDR bit is cleared (output), the digital
output level (V
OH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS2:CHS0 bits and the DDR bits.
16.4 A/D Conversions
Example 16-2 shows how to perform an A/D conver-
sion. The PORTF and lower four PORTG pins are con-
figured as analog inputs. The analog references
(V
REF+ and VREF-) are the device AVDD and AVSS. The
A/D interrupt is enabled, and the A/D conversion clock
is F
RC. The conversion is performed on the RG3/AN0
pin (channel 0).
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed A/
D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2T
AD wait is required before the next
acquisition is started. After this 2T
AD wait, acquisition
on the selected channel is automatically started.
In Figure 16-4, after the GO bit is set, the first time seg-
ment has a minimum of T
CY and a maximum of TAD.
EXAMPLE 16-2: A/D CONVERSION
FIGURE 16-4: A/D CONVERSION T
AD CYCLES
Note 1: When reading the port register, any pin
configured as an analog input channel will
read as cleared (a low level). Pins config-
ured as digital inputs, will convert an ana-
log input. Analog levels on a digitally
configured input will not affect the conver-
sion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN15:AN0
pins), may cause the input buffer to con-
sume current that is out of the devices
specification.
Note: The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
MOVLB 5 ; Bank 5
CLRF ADCON1, F ; Configure A/D inputs, All analog, TAD = Fosc/8, left just.
MOVLW 0x01 ; A/D is on, Channel 0 is selected
MOVWF ADCON0 ;
MOVLB 4 ; Bank 4
BCF PIR2, ADIF ; Clear A/D interrupt flag bit
BSF PIE2, ADIE ; Enable A/D interrupts
BSF INTSTA, PEIE ; Enable peripheral interrupts
BCF CPUSTA, GLINTD ; Enable all interrupts
;
; Ensure that the required sampling time for the selected input channel has elapsed.
; Then the conversion may be started.
;
MOVLB 5 ; Bank 5
BSF ADCON0, GO ; Start A/D Conversion
: ; The ADIF bit will be set and the GO/DONE bit
: ; is cleared upon completion of the A/D Conversion
TAD1
TAD2
TAD3
TAD4 TAD5
TAD6 TAD7
TAD8
TAD9
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns).
holding capacitor is connected to analog input.
b9
b8
b7 b6
b5
b4
b3
b2
TAD10
TAD11
b1
b0
TCY to TAD
GO bit is cleared,
Next Q4: ADRES is loaded,
ADIF bit is set,
Conversion starts.