Datasheet

PIC17C7XX
DS30289C-page 126  1998-2013 Microchip Technology Inc.
Steps to follow when setting up an Asynchronous
Reception:
1. Initialize the SPBRG register for the appropriate
baud rate.
2. Enable the asynchronous serial port by clearing
the SYNC bit and setting the SPEN bit.
3. If interrupts are desired, then set the RCIE bit.
4. If 9-bit reception is desired, then set the RX9 bit.
5. Enable the reception by setting the CREN bit.
6. The RCIF bit will be set when reception com-
pletes and an interrupt will be generated if the
RCIE bit was set.
7. Read RCSTA to get the ninth bit (if enabled) and
FERR bit to determine if any error occurred dur-
ing reception.
8. Read RCREG for the 8-bit received data.
9. If an overrun error occurred, clear the error by
clearing the OERR bit.
FIGURE 14-7: ASYNCHRONOUS RECEPTION
TABLE 14-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
Note: To terminate a reception, either clear the
SREN and CREN bits, or the SPEN bit.
This will reset the receive logic, so that it
will be in the proper state when receive is
re-enabled.
START
bit
bit7/8
bit1bit0
bit7/8 bit0STOP
bit
START
bit
START
bit
bit7/8
STOP
bit
RX
Reg
Rcv Buffer Reg
Rcv Shift
Read Rcv
Buffer Reg
RCREG
RCIF
(Interrupt Flag)
OERR bit
CREN
Word 1
RCREG
Word 2
RCREG
STOP
bit
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
(RX/DT pin)
Word 3
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
MCLR, WDT
16h, Bank 1 PIR1
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN
— FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 0 TXSTA1
CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 0 SPBRG1 Baud Rate Generator Register 0000 0000 0000 0000
10h, Bank 4 PIR2
SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2
SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE 000- 0000 000- 0000
13h, Bank 4 RCSTA2 SPEN RX9 SREN CREN
— FERR OERR RX9D 0000 -00x 0000 -00u
14h, Bank 4 RCREG2 RX7 RX6 RX5 RX4 RX3 RX2 RX1 RX0 xxxx xxxx uuuu uuuu
15h, Bank 4 TXSTA2
CSRC TX9 TXEN SYNC — — TRMT TX9D 0000 --1x 0000 --1u
17h, Bank 4 SPBRG2 Baud Rate Generator Register 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as a '0'. Shaded cells are not used for asynchronous reception.