Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 119
PIC17C7XX
FIGURE 14-1: USART TRANSMIT
FIGURE 14-2: USART RECEIVE
CK/TX
DT
Sync/Async
TSR
Start 0 1 7 8 Stop

 16
 4BRG
01 7

8 Bit Count
TXIE
Interrupt
TXEN/
Write to TXREG
Clock
Sync/Async
Sync/Async
TXSTA<0>
Sync
Master/Slave
Data Bus
Load
TXREG
CK
RX
0178Stop

 16
 4
BRG
Bit Count
Clock
Buffer
Logic
Buffer
Logic
SPEN
OSC
START
017RX9D

017RX9D

FERR
FERR
Majority
Detect
Data
MSb LSb
RSR
RCREG
Async/Sync
Sync/Async
Master/Slave
Sync
Enable
FIFO
Logic
Clk
FIFO
RCIE
Interrupt
RX9
Data Bus
SREN/
CREN/
Start_Bit
Async/Sync
Detect