Datasheet
1998-2013 Microchip Technology Inc. DS30289C-page 113
PIC17C7XX
13.2.3 READING THE CAPTURE
REGISTERS
The Capture overflow status flag bits are double buff-
ered. The master bit is set if one captured word is
already residing in the Capture register and another
“event” has occurred on the CAPx pin. The new event
will not transfer the TMR3 value to the capture register,
protecting the previous unread capture value. When
the user reads both the high and the low bytes (in any
order) of the Capture register, the master overflow bit is
transferred to the slave overflow bit (CAxOVF) and
then the master bit is reset. The user can then read
TCONx to determine the value of CAxOVF.
An example of an instruction sequence to read capture
registers and capture overflow flag bits is shown in
Example 13-1. Depending on the capture source, dif-
ferent registers will need to be read.
EXAMPLE 13-1: SEQUENCE TO READ CAPTURE REGISTERS
TABLE 13-6: REGISTERS ASSOCIATED WITH CAPTURE
MOVLB 3 ; Select Bank 3
MOVPF CA2L, LO_BYTE ; Read Capture2 low byte, store in LO_BYTE
MOVPF CA2H, HI_BYTE ; Read Capture2 high byte, store in HI_BYTE
MOVPF TCON2, STAT_VAL ; Read TCON2 into file STAT_VAL
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
MCLR, WDT
16h, Bank 3 TCON1 CA2ED1 CA2ED0 CA1ED1 CA1ED0
T16 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000
17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000
16h, Bank 7 TCON3
— CA4OVF CA3OVF CA4ED1 CA4ED0 CA3ED1 CA3ED0 PWM3ON
-000 0000 -000 0000
12h, Bank 2 TMR3L Holding Register for the Low Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
13h, Bank 2 TMR3H Holding Register for the High Byte of the 16-bit TMR3 Register xxxx xxxx uuuu uuuu
16h, Bank 1 PIR1
RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010
17h, Bank 1 PIE1
RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000
10h, Bank 4 PIR2
SSPIF BCLIF ADIF —CA4IFCA3IFTX2IF RC2IF 000- 0010 000- 0010
11h, Bank 4 PIE2
SSPIE BCLIE ADIE —CA4IECA3IETX2IE RC2IE 000- 0000 000- 0000
07h, Unbanked INTSTA PEIF
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
06h, Unbanked CPUSTA
— — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
16h, Bank 2 PR3L/CA1L Timer3 Period Register, Low Byte/Capture1 Register, Low Byte xxxx xxxx uuuu uuuu
17h, Bank 2 PR3H/CA1H Timer3 Period Register, High Byte/Capture1 Register, High Byte xxxx xxxx uuuu uuuu
14h, Bank 3 CA2L Capture2 Low Byte xxxx xxxx uuuu uuuu
15h, Bank 3 CA2H Capture2 High Byte xxxx xxxx uuuu uuuu
12h, Bank 7 CA3L Capture3 Low Byte xxxx xxxx uuuu uuuu
13h, Bank 7 CA3H Capture3 High Byte xxxx xxxx uuuu uuuu
14h, Bank 7 CA4L Capture4 Low Byte xxxx xxxx uuuu uuuu
15h, Bank 7 CA4H Capture4 High Byte xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are not used by Capture.