PIC17C7XX High-Performance 8-bit CMOS EPROM Microcontrollers with 10-bit A/D • Only 58 single word instructions to learn • All single cycle instructions (121 ns), except for program branches and table reads/writes which are two-cycle • Operating speed: - DC - 33 MHz clock input - DC - 121 ns instruction cycle • 8 x 8 Single-Cycle Hardware Multiplier • Interrupt capability • 16 level deep hardware stack • Direct, indirect, and relative addressing modes • Internal/external program memory execution, capable o
PIC17C7XX RD2/AD10 RD3/AD11 RD4/AD12 RD5/AD13 RD6/AD14 RD7/AD15 RC0/AD0 VDD NC VSS RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/AD5 RC6/AD6 RC7/AD7 Pin Diagrams cont.
PIC17C7XX Pin Diagrams cont.
PIC17C7XX Table of Contents 1.0 Overview ........................................................................................................................................................ 7 2.0 Device Varieties ............................................................................................................................................. 9 3.0 Architectural Overview ............................................................................................................................
PIC17C7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.
PIC17C7XX NOTES: DS30289C-page 6 1998-2013 Microchip Technology Inc.
PIC17C7XX 1.0 OVERVIEW This data sheet covers the PIC17C7XX group of the PIC17CXXX family of microcontrollers. The following devices are discussed in this data sheet: • • • • PIC17C752 PIC17C756A PIC17C762 PIC17C766 The PIC17C7XX devices are 68/84-pin, EPROM based members of the versatile PIC17CXXX family of low cost, high performance, CMOS, fully static, 8-bit microcontrollers. All PIC® microcontrollers employ an advanced RISC architecture.
PIC17C7XX TABLE 1-1: PIC17CXXX FAMILY OF DEVICES Features Maximum Frequency of Operation PIC17C42A PIC17C43 PIC17C44 PIC17C752 PIC17C756A PIC17C762 PIC17C766 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 2.5 - 6.0V 2.5 - 6.0V 2.5 - 6.0V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.5V 3.0 - 5.
PIC17C7XX 2.0 DEVICE VARIETIES 2.3 Each device has a variety of frequency ranges and packaging options. Depending on application and production requirements, the proper device option can be selected using the information in the PIC17C7XX Product Selection System section at the end of this data sheet. When placing orders, please use the “PIC17C7XX Product Identification System” at the back of this data sheet to specify the correct part number.
PIC17C7XX NOTES: DS30289C-page 10 1998-2013 Microchip Technology Inc.
PIC17C7XX 3.0 ARCHITECTURAL OVERVIEW The high performance of the PIC17CXXX can be attributed to a number of architectural features, commonly found in RISC microprocessors. To begin with, the PIC17CXXX uses a modified Harvard architecture. This architecture has the program and data accessed from separate memories. So, the device has a program memory bus and a data memory bus.
PIC17C7XX FIGURE 3-1: PIC17C752/756A BLOCK DIAGRAM PORTA RA0/INT RA1/T0CKI RA2/SS/SCL RA3/SDI/SDA RA4/RX1/DT1 RA5/TX1/CK1 WREG<8> IR<16> BITOP Clock Generator Q1, Q2, Q3, Q4 OSC1, OSC2 Power-on Reset Brown-out VDD, VSS Reset PORTB 8 x 8 mult RB0/CAP1 RB1/CAP2 RB2/PWM1 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB6/SCK RB7/SDO Chip_reset & Other Control Signals ALU PRODH PRODL Shifter Watchdog Timer MCLR, VPP Test Mode Select Test IR Latch <16> 8 8 8 BSR <7:4> IR <7:0> PORTC RC0/AD0 RC1/AD1 RC2/AD
PIC17C7XX PIC17C762/766 BLOCK DIAGRAM PORTA Clock Generator RA0/INT RA1/T0CKI RA2/SS/SCL RA3/SDI/SDA RA4/RX1/DT1 RA5/TX1/CK1 WREG<8> Q1, Q2, Q3, Q4 IR<16> BITOP Chip_reset & Other Control Signals PORTB RB0/CAP1 RB1/CAP2 RB2/PWM1 RB3/PWM2 RB4/TCLK12 RB5/TCLK3 RB6/SCK RB7/SDO 8 x 8 mult ALU OSC1, OSC2 Power-on Reset Watchdog Timer VDD, VSS Test Mode Select MCLR, VPP Brown-out Reset Test AVDD, AVSS PRODH PRODL Shifter IR Latch <16> PORTC 8 8 RC0/AD0 RC1/AD1 RC2/AD2 RC3/AD3 RC4/AD4 RC5/A
PIC17C7XX TABLE 3-1: PINOUT DESCRIPTIONS PIC17C75X Name PIC17C76X DIP No. PLCC No. TQFP No. PLCC No. QFP No. I/O/P Type Buffer Type Description OSC1/CLKIN 47 50 39 62 49 I ST Oscillator input in Crystal/Resonator or RC Oscillator mode. External clock input in External Clock mode. OSC2/CLKOUT 48 51 40 63 50 O — Oscillator output. Connects to crystal or resonator in Crystal Oscillator mode.
PIC17C7XX TABLE 3-1: PINOUT DESCRIPTIONS (CONTINUED) PIC17C75X Name PIC17C76X DIP No. PLCC No. TQFP No. PLCC No. QFP No.
PIC17C7XX TABLE 3-1: PINOUT DESCRIPTIONS (CONTINUED) PIC17C75X Name PIC17C76X Description DIP No. PLCC No. TQFP No. PLCC No. QFP No. I/O/P Type Buffer Type RG0/AN3 32 34 24 42 30 I/O ST RG0 can also be analog input 3. RG1/AN2 31 33 23 41 29 I/O ST RG1 can also be analog input 2. RG2/AN1/VREF- 30 32 22 40 28 I/O ST RG2 can also be analog input 1, or the ground reference voltage.
PIC17C7XX 4.0 ON-CHIP OSCILLATOR CIRCUIT The internal oscillator circuit is used to generate the device clock. Four device clock periods generate an internal instruction clock (TCY). There are four modes that the oscillator can operate in. They are selected by the device configuration bits during device programming.
PIC17C7XX FIGURE 4-2: CRYSTAL OR CERAMIC RESONATOR OPERATION (XT OR LF OSC CONFIGURATION) FIGURE 4-3: CRYSTAL OPERATION, OVERTONE CRYSTALS (XT OSC CONFIGURATION) C1 OSC1 OSC1 C1 XTAL SLEEP SLEEP RF C2 OSC2 OSC2 (Note 1) To internal logic C2 See Table 4-1 and Table 4-2 for recommended values of C1 and C2. A series resistor (Rs) may be required for AT strip cut crystals. TABLE 4-1: L1 PIC17CXXX 0.
PIC17C7XX 4.1.4 EXTERNAL CLOCK OSCILLATOR FIGURE 4-5: In the EC oscillator mode, the OSC1 input can be driven by CMOS drivers. In this mode, the OSC1/ CLKIN pin is hi-impedance and the OSC2/CLKOUT pin is the CLKOUT output (4 TOSC). FIGURE 4-4: EXTERNAL PARALLEL RESONANT CRYSTAL OSCILLATOR CIRCUIT +5V To Other Devices 10 k 4.7 k EXTERNAL CLOCK INPUT OPERATION (EC OSC CONFIGURATION) PIC17CXXX OSC1 74AS04 10 k Clock from OSC1 ext. system CLKOUT (FOSC/4) XTAL PIC17CXXX OSC2 10k 20 pF 4.1.
PIC17C7XX 4.1.6 RC OSCILLATOR For timing insensitive applications, the RC device option offers additional cost savings. RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, oscillator frequency will vary from unit to unit due to normal process parameter variation.
PIC17C7XX 4.2 Clocking Scheme/Instruction Cycle 4.3 Instruction Flow/Pipelining An “Instruction Cycle” consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle, while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC17C7XX NOTES: DS30289C-page 22 1998-2013 Microchip Technology Inc.
PIC17C7XX 5.0 RESET The PIC17CXXX differentiates between various kinds of RESET: • • • • Power-on Reset (POR) Brown-out Reset MCLR Reset WDT Reset Note: Some registers are not affected in any RESET condition, their status is unknown on POR and unchanged in any other RESET. Most other registers are forced to a “RESET state”. The TO and PD bits are set or cleared differently in different RESET situations, as indicated in Table 5-3.
PIC17C7XX 5.1 Power-on Reset (POR), Power-up Timer (PWRT), Oscillator Start-up Timer (OST) and Brown-out Reset (BOR) 5.1.1 POWER-ON RESET (POR) The Power-on Reset circuit holds the device in RESET until VDD is above the trip point (in the range of 1.4V 2.3V). The devices produce an internal RESET for both rising and falling VDD. To take advantage of the POR, just tie the MCLR/VPP pin directly (or through a resistor) to VDD.
PIC17C7XX 5.1.4 TIME-OUT SEQUENCE If the device voltage is not within electrical specification at the end of a time-out, the MCLR/VPP pin must be held low until the voltage is within the device specification. The use of an external RC delay is sufficient for many of these applications. On power-up, the time-out sequence is as follows: First, the internal POR signal goes high when the POR trip point is reached. If MCLR is high, then both the OST and PWRT timers start.
PIC17C7XX In Figure 5-5, Figure 5-6 and Figure 5-7, the TPWRT timer time-out is greater then the TOST timer time-out, as would be the case in higher frequency crystals. For lower frequency crystals (i.e., 32 kHz), TOST may be greater.
PIC17C7XX TABLE 5-4: Register INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS Address Power-on Reset Brown-out Reset MCLR Reset WDT Reset Wake-up from SLEEP through Interrupt Unbanked INDF0 00h N/A N/A N/A FSR0 01h xxxx xxxx uuuu uuuu uuuu uuuu PCL 02h 0000h 0000h PCLATH 03h 0000 0000 uuuu uuuu uuuu uuuu ALUSTA 04h 1111 xxxx 1111 uuuu 1111 uuuu T0STA 05h 0000 000- 0000 000- 0000 000- 06h --11 11qq --11 qquu --uu qquu 07h 0000 0000 0000 0000 uuuu uuuu(1) CPU
PIC17C7XX TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED) Address Power-on Reset Brown-out Reset MCLR Reset WDT Reset Wake-up from SLEEP through Interrupt DDRC(5) 10h 1111 1111 1111 1111 uuuu uuuu PORTC(4,5) 11h xxxx xxxx uuuu uuuu uuuu uuuu DDRD(5) 12h 1111 1111 1111 1111 uuuu uuuu PORTD(4,5) 13h xxxx xxxx uuuu uuuu uuuu uuuu DDRE(5) 14h ---- 1111 ---- 1111 ---- uuuu PORTE(4,5) 15h ---- xxxx ---- uuuu ---- uuuu PIR1 16h x000 0010 u000 00
PIC17C7XX TABLE 5-4: Register INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED) Address Power-on Reset Brown-out Reset MCLR Reset WDT Reset 10h 000- 0010 000- 0010 Wake-up from SLEEP through Interrupt Bank 4 PIR2 uuu- uuuu(1) PIE2 11h 000- 0000 000- 0000 uuu- uuuu Unimplemented 12h ---- ---- ---- ---- ---- ---- RCSTA2 13h 0000 -00x 0000 -00u uuuu -uuu RCREG2 14h xxxx xxxx uuuu uuuu uuuu uuuu TXSTA2 15h 0000 --1x 0000 --1u uuuu --uu TXREG2 16h xxxx xxxx
PIC17C7XX TABLE 5-4: INITIALIZATION CONDITIONS FOR SPECIAL FUNCTION REGISTERS (CONTINUED) Address Power-on Reset Brown-out Reset MCLR Reset WDT Reset Wake-up from SLEEP through Interrupt PW3DCL 10h xx0- ---- uu0- ---- uuu- ---- PW3DCH 11h xxxx xxxx uuuu uuuu uuuu uuuu CA3L 12h xxxx xxxx uuuu uuuu uuuu uuuu CA3H 13h xxxx xxxx uuuu uuuu uuuu uuuu CA4L 14h xxxx xxxx uuuu uuuu uuuu uuuu CA4H 15h xxxx xxxx uuuu uuuu uuuu uuuu Register Bank 7 TCON3 16h -000 0000 -000 0000 -
PIC17C7XX 5.1.5 BROWN-OUT RESET (BOR) that may be implemented. Each needs to be evaluated to determine if they match the requirements of the application. PIC17C7XX devices have on-chip Brown-out Reset circuitry. This circuitry places the device into a RESET when the device voltage falls below a trip point (BVDD). This ensures that the device does not continue program execution outside the valid operation range of the device.
PIC17C7XX NOTES: DS30289C-page 32 1998-2013 Microchip Technology Inc.
PIC17C7XX 6.
PIC17C7XX 6.1 Interrupt Status Register (INTSTA) Care should be taken when clearing any of the INTSTA register enable bits when interrupts are enabled (GLINTD is clear). If any of the INTSTA flag bits (T0IF, INTF, T0CKIF, or PEIF) are set in the same instruction cycle as the corresponding interrupt enable bit is cleared, the device will vector to the RESET address (0x00). The Interrupt Status/Control register (INTSTA) contains the flag and enable bits for non-peripheral interrupts.
PIC17C7XX 6.2 Peripheral Interrupt Enable Register1 (PIE1) and Register2 (PIE2) These registers contains the individual enable bits for the peripheral interrupts.
PIC17C7XX REGISTER 6-3: PIE2 REGISTER (ADDRESS: 11h, BANK 4) R/W-0 SSPIE R/W-0 BCLIE R/W-0 ADIE U-0 — R/W-0 CA4IE R/W-0 CA3IE R/W-0 TX2IE bit 7 R/W-0 RC2IE bit 0 bit 7 SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enable SSP interrupt 0 = Disable SSP interrupt bit 6 BCLIE: Bus Collision Interrupt Enable bit 1 = Enable bus collision interrupt 0 = Disable bus collision interrupt bit 5 ADIE: A/D Module Interrupt Enable bit 1 = Enable A/D module interrupt 0 = Disable A/D module interrupt
PIC17C7XX 6.3 Peripheral Interrupt Request Register1 (PIR1) and Register2 (PIR2) Note: These registers contains the individual flag bits for the peripheral interrupts. These bits will be set by the specified condition, even if the corresponding interrupt enable bit is cleared (interrupt disabled), or the GLINTD bit is set (all interrupts disabled).
PIC17C7XX REGISTER 6-5: PIR2 REGISTER (ADDRESS: 10h, BANK 4) R/W-0 SSPIF R/W-0 BCLIF R/W-0 ADIF U-0 — R/W-0 CA4IF R/W-0 CA3IF R-1 TX2IF bit 7 bit 7 R-0 RC2IF bit 0 SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit 1 = The SSP interrupt condition has occurred and must be cleared in software before returning from the Interrupt Service Routine. The conditions that will set this bit are: SPI: A transmission/reception has taken place. I2 C Slave/Master: A transmission/reception has taken place.
PIC17C7XX 6.4 Interrupt Operation 6.5 Global Interrupt Disable bit, GLINTD (CPUSTA<4>), enables all unmasked interrupts (if clear), or disables all interrupts (if set). Individual interrupts can be disabled through their corresponding enable bits in the INTSTA register. Peripheral interrupts need either the global peripheral enable PEIE bit disabled, or the specific peripheral enable bit disabled. Disabling the peripherals via the global peripheral enable bit, disables all peripheral interrupts.
DS30289C-page 40 Instruction Executed System Bus Instruction Fetched PC GLINTD INTF or T0CKIF RA0/INT or RA1/T0CKI PC Q2 PC Q4 Inst (PC) Q3 Q1 Q4 Inst (PC+1) PC + 1 Q3 Inst (PC) Addr Q2 Q1 Q4 Inst (PC+1) Q3 Dummy Addr Q2 Q1 Q3 Q4 Dummy Addr Inst (Vector) Addr (Vector) Q2 Q1 Addr Q2 YY Q4 RETFIE Q3 Q1 Q3 Q4 Inst (YY + 1) RETFIE Addr YY + 1 Q2 Q1 Q3 Dummy PC + 1 Q2 Q4 FIGURE 6-2: OSC2 OSC1 Q1 PIC17C7XX INT PIN/T0CKI PIN INTERRUPT TIMING 1998-2013
PIC17C7XX EXAMPLE 6-1: SAVING STATUS AND WREG IN RAM (SIMPLE) ; The addresses that are used to store the CPUSTA and WREG values must be in the data memory ; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP ; instruction. This instruction neither affects the status bits, nor corrupts the WREG register.
PIC17C7XX EXAMPLE 6-2: SAVING STATUS AND WREG IN RAM (NESTED) ; The addresses that are used to store the CPUSTA and WREG values must be in the data memory ; address range of 1Ah - 1Fh. Up to 6 locations can be saved and restored using the MOVFP ; instruction. This instruction neither affects the status bits, nor corrupts the WREG register. ; This routine uses the FRS0, so it controls the FS1 and FS0 bits in the ALUSTA register.
PIC17C7XX 7.0 MEMORY ORGANIZATION There are two memory blocks in the PIC17C7XX; program memory and data memory. Each block has its own bus, so that access to each block can occur during the same oscillator cycle. The data memory can further be broken down into General Purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC17C7XX MODE MEMORY ACCESS Internal Program Memory Configuration Bits, Test Memory, Boot ROM Microprocessor No Access No Access Microcontroller Access Access Extended Microcontroller Access No Access Protected Microcontroller Access Access MEMORY MAP IN DIFFERENT MODES Extended Microcontroller Mode Microcontroller Modes 0000h 0000h 0000h 01FFFh On-chip Program Memory 01FFFh 2000h 2000h External Program Memory External Program Memory PIC17C752/762 FE00h Config.
PIC17C7XX 7.1.2 EXTERNAL MEMORY INTERFACE When either Microprocessor or Extended Microcontroller mode is selected, PORTC, PORTD and PORTE are configured as the system bus. PORTC and PORTD are the multiplexed address/data bus and PORTE<2:0> is for the control signals. External components are needed to demultiplex the address and data. This can be done as shown in Figure 7-4. The waveforms of address and data are shown in Figure 7-3.
PIC17C7XX 7.2 Data Memory Organization Data memory is partitioned into two areas. The first is the General Purpose Registers (GPR) area, and the second is the Special Function Registers (SFR) area. The SFRs control and provide status of device operation. Portions of data memory are banked, this occurs in both areas. The GPR area is banked to allow greater than 232 bytes of general purpose RAM. Banking requires the use of control bits for bank selection.
PIC17C7XX FIGURE 7-5: Addr Unbanked 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh INDF0 10h 11h 12h 13h 14h 15h 16h 17h PIC17C7XX REGISTER FILE MAP FSR0 PCL PCLATH ALUSTA T0STA CPUSTA INTSTA INDF1 FSR1 WREG TMR0L TMR0H TBLPTRL TBLPTRH BSR Bank 0 Bank 1(1) Bank 2(1) Bank 3(1) Bank 4(1) Bank 5(1) Bank 6(1) Bank 7(1) Bank 8(1,4) PORTA DDRC TMR1 PW1DCL PIR2 DDRF SSPADD PW3DCL DDRH PORTH DDRB PORTC TMR2 PW2DCL PIE2 PORTF SSPCON1 PW3DCH PORTB DDRD TMR3L PW1DCH
PIC17C7XX TABLE 7-3: Address SPECIAL FUNCTION REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Unbanked 00h INDF0 01h FSR0 02h PCL Uses contents of FSR0 to address Data Memory (not a physical register) Indirect Data Memory Address Pointer 0 Low order 8-bits of PC 03h(1) 04h 05h PCLATH ALUSTA T0STA Holding Register for upper 8-bits of PC FS3 FS2 FS1 FS0 INTEDG T0SE T0CS T0PS3 06h(2) CPUSTA INTSTA INDF1 FSR1 WREG TMR0L TMR0H TBLPTRL TBLPTRH BSR — — STKAV GLINTD TO PD PEIF T0CKIF T0IF
PIC17C7XX TABLE 7-3: Address SPECIAL FUNCTION REGISTERS (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bank 2 10h 11h 12h 13h 14h 15h 16h 17h TMR1 TMR2 TMR3L TMR3H PR1 PR2 PR3L/CA1L PR3H/CA1H Timer1’s Register Timer2’s Register Timer3’s Register; Low Byte Timer3’s Register; High Byte Timer1’s Period Register Timer2’s Period Register Timer3’s Period Register - Low Byte/Capture1 Register; Low Byte Timer3’s Period Register - High Byte/Capture1 Register; High Byte Bank 3 10h 11h 12h 13h 14h 15
PIC17C7XX TABLE 7-3: Address SPECIAL FUNCTION REGISTERS (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR MCLR, WDT Bank 6 SSP Address Register in I2C Slave mode.
PIC17C7XX 7.2.2.1 ALU Status Register (ALUSTA) The ALUSTA register contains the status bits of the Arithmetic and Logic Unit and the mode control bits for the indirect addressing register. As with all the other registers, the ALUSTA register can be the destination for any instruction. If the ALUSTA register is the destination for an instruction that affects the Z, DC, C, or OV bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC17C7XX 7.2.2.2 CPU Status Register (CPUSTA) The CPUSTA register contains the status and control bits for the CPU. This register has a bit that is used to globally enable/disable interrupts. If only a specific interrupt is desired to be enabled/disabled, please refer to the Interrupt Status (INTSTA) register and the Peripheral Interrupt Enable (PIE) registers. The CPUSTA register also indicates if the stack is available and contains the Power-down (PD) and Time-out (TO) bits.
PIC17C7XX 7.2.2.3 TMR0 Status/Control Register (T0STA) This register contains various control bits. Bit7 (INTEDG) is used to control the edge upon which a signal on the RA0/INT pin will set the RA0/INT interrupt flag. The other bits configure Timer0, it’s prescaler and clock source.
PIC17C7XX 7.3 Stack Operation PIC17C7XX devices have a 16 x 16-bit hardware stack (Figure 7-1). The stack is not part of either the program or data memory space, and the stack pointer is neither readable nor writable. The PC (Program Counter) is “PUSH’d” onto the stack when a CALL or LCALL instruction is executed, or an interrupt is acknowledged. The stack is “POP’d” in the event of a RETURN, RETLW, or a RETFIE instruction execution. PCLATH is not affected by a “PUSH” or a “POP” operation.
PIC17C7XX 7.4.2 INDIRECT ADDRESSING OPERATION 7.5 Table Pointer (TBLPTRL and TBLPTRH) The indirect addressing capability has been enhanced over that of the PIC16CXX family. There are two control bits associated with each FSR register. These two bits configure the FSR register to: File registers TBLPTRL and TBLPTRH form a 16-bit pointer to address the 64K program memory space. The table pointer is used by instructions TABLWT and TABLRD.
PIC17C7XX 7.7 Program Counter Module The Program Counter (PC) is a 16-bit register. PCL, the low byte of the PC, is mapped in the data memory. PCL is readable and writable just as is any other register. PCH is the high byte of the PC and is not directly addressable. Since PCH is not mapped in data or program memory, an 8-bit register PCLATH (PC high latch) is used as a holding latch for the high byte of the PC. PCLATH is mapped into data memory. The user can read or write PCH through PCLATH.
PIC17C7XX 7.8 Bank Select Register (BSR) bank in order to address all peripherals related to a single task. To assist this, a MOVLB bank instruction has been included in the instruction set. The BSR is used to switch between banks in the data memory area (Figure 7-9). In the PIC17C7XX devices, the entire byte is implemented. The lower nibble is used to select the peripheral register bank. The upper nibble is used to select the general purpose memory bank.
PIC17C7XX NOTES: DS30289C-page 58 1998-2013 Microchip Technology Inc.
PIC17C7XX 8.0 TABLE READS AND TABLE WRITES FIGURE 8-2: The PIC17C7XX has four instructions that allow the processor to move data from the data memory space to the program memory space, and vice versa. Since the program memory space is 16-bits wide and the data memory space is 8-bits wide, two operations are required to move 16-bit values to/from the data memory. The TLWT t,f and TABLWT t,i,f instructions are used to write data from the data memory space to the program memory space.
PIC17C7XX FIGURE 8-3: TLRD INSTRUCTION OPERATION FIGURE 8-4: TABLE POINTER TABLE POINTER TBLPTRH TBLPTRH TBLPTRL TLRD 1,f TBLPTRL TABLE LATCH (16-bit) TABLE LATCH (16-bit) TABLATH TABLRD INSTRUCTION OPERATION TABLATH TABLATL TABLATL TLRD 0,f 3 TABLRD 0,i,f 3 TABLRD 1,i,f Data Memory Program Memory Data Memory f Program Memory 1 f 1 Prog-Mem (TBLPTR) 2 Step 1: 8-bit value from TABLAT (16-bit) high or low byte, loaded into register 'f'.
PIC17C7XX 8.1 8.1.1 Table Writes to Internal Memory A table write operation to internal memory causes a long write operation. The long write is necessary for programming the internal EPROM. Instruction execution is halted while in a long write cycle. The long write will be terminated by any enabled interrupt. To ensure that the EPROM location has been well programmed, a minimum programming time is required (see specification #D114).
PIC17C7XX 8.2 Table Writes to External Memory EXAMPLE 8-1: Table writes to external memory are always two-cycle instructions. The second cycle writes the data to the external memory location. The sequence of events for an external memory write are the same for an internal write. 8.2.1 TABLE WRITE CODE The “i” operand of the TABLWT instruction can specify that the value in the 16-bit TBLPTR register is automatically incremented (for the next write).
PIC17C7XX FIGURE 8-6: CONSECUTIVE TABLWT WRITE TIMING (EXTERNAL MEMORY) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 AD15:AD0 PC Instruction Fetched TABLWT1 Instruction Executed INST (PC-1) PC+1 TBL1 Data out 1 TABLWT2 PC+2 TBL2 Data out 2 INST (PC+2) INST (PC+3) TABLWT1 cycle1 TABLWT1 cycle2 TABLWT2 cycle1 TABLWT2 cycle2 Data write cycle PC+3 INST (PC+2) Data write cycle ALE OE WR 1998-2013 Microchip Technology Inc.
PIC17C7XX 8.3 EXAMPLE 8-2: Table Reads The table read allows the program memory to be read. This allows constants to be stored in the program memory space and retrieved into data memory when needed. Example 8-2 reads the 16-bit value at program memory address TBLPTR. After the dummy byte has been read from the TABLATH, the TABLATH is loaded with the 16-bit data from program memory address TBLPTR and then increments the TBLPTR value.
PIC17C7XX 8.4 Operation with External Memory Interface When the table reads/writes are accessing external memory (via the external system interface bus), the table latch for the table reads is different from the table latch for the table writes (see Figure 8-9). This means that you cannot do a TABLRD instruction, and use the values that were loaded into the table latches for a TABLWT instruction. Any table write sequence should use both the TLWT and then the TABLWT instructions.
PIC17C7XX NOTES: DS30289C-page 66 1998-2013 Microchip Technology Inc.
PIC17C7XX 9.0 HARDWARE MULTIPLIER Example 9-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument’s most significant bit (MSb) is tested and the appropriate subtractions are done. All PIC17C7XX devices have an 8 x 8 hardware multiplier included in the ALU of the device. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result.
PIC17C7XX Example 9-3 shows the sequence to do a 16 x 16 unsigned multiply. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in 4 registers, RES3:RES0.
PIC17C7XX Example 9-4 shows the sequence to do a 16 x 16 signed multiply. Equation 9-2 shows the algorithm used. The 32-bit result is stored in four registers, RES3:RES0. To account for the sign bits of the arguments, each argument pairs most significant bit (MSb) is tested and the appropriate subtractions are done.
PIC17C7XX NOTES: DS30289C-page 70 1998-2013 Microchip Technology Inc.
PIC17C7XX 10.0 I/O PORTS PIC17C75X devices have seven I/O ports, PORTA through PORTG. PIC17C76X devices have nine I/O ports, PORTA through PORTJ. PORTB through PORTJ have a corresponding Data Direction Register (DDR), which is used to configure the port pins as inputs or outputs. Some of these ports pins are multiplexed with alternate functions. PORTC, PORTD, and PORTE are multiplexed with the system bus.
PIC17C7XX 10.1 PORTA Register PORTA is a 6-bit wide latch. PORTA does not have a corresponding Data Direction Register (DDR). Upon a device RESET, the PORTA pins are forced to be hiimpedance inputs. For the RA4 and RA5 pins, the peripheral module controls the output. When a device RESET occurs, the peripheral module is disabled, so these pins are forced to be hi-impedance inputs. Reading PORTA reads the status of the pins. The RA0 pin is multiplexed with the external interrupt, INT.
PIC17C7XX FIGURE 10-3: RA3 BLOCK DIAGRAM FIGURE 10-4: Peripheral Data In RA4 AND RA5 BLOCK DIAGRAM Serial Port Input Signal D Q Data Bus EN Data Bus RD_PORTA (Q2) RD_PORTA (Q2) Q D Q Serial Port Output Signals WR_PORTA (Q4) SDA Out CK OE = SPEN,SYNC,TXEN, CREN, SREN for RA4 OE = SPEN (SYNC+SYNC, CSRC) for RA5 '1' Note: I/O pins have protection diodes to VDD and VSS. SSP Mode Note: I/O pin has protection diodes to VSS.
PIC17C7XX 10.2 PORTB and DDRB Registers This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt by: PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is DDRB. A '1' in DDRB configures the corresponding port pin as an input. A '0' in the DDRB register configures the corresponding port pin as an output. Reading PORTB reads the status of the pins, whereas writing to PORTB will write to the port latch.
PIC17C7XX EXAMPLE 10-2: Example 10-2 shows an instruction sequence to initialize PORTB. The Bank Select Register (BSR) must be selected to Bank 0 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection.
PIC17C7XX FIGURE 10-7: BLOCK DIAGRAM OF RB6 PORT PIN Peripheral Data In RBPU (PORTA<7>) Weak Pull-up Match Signal from other port pins RBIF D Q Data Bus EN RD_DDRB (Q2) RD_PORTB (Q2) D OE Q WR_DDRB (Q4) CK P Port Data 0 Q D 1 Q WR_PORTB (Q4) CK N SPI Output SPI Output Enable Note: I/O pin has protection diodes to Vdd and Vss.
PIC17C7XX TABLE 10-3: PORTB FUNCTIONS Name Bit Buffer Type Function RB0/CAP1 bit0 ST Input/output or the Capture1 input pin. Software programmable weak pull-up and interrupt-on-change features. RB1/CAP2 bit1 ST Input/output or the Capture2 input pin. Software programmable weak pull-up and interrupt-on-change features. RB2/PWM1 bit2 ST Input/output or the PWM1 output pin. Software programmable weak pull-up and interrupt-on-change features.
PIC17C7XX 10.3 PORTC and DDRC Registers Example 10-3 shows an instruction sequence to initialize PORTC. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection. PORTC is an 8-bit bi-directional port. The corresponding data direction register is DDRC. A '1' in DDRC configures the corresponding port pin as an input.
PIC17C7XX TABLE 10-5: PORTC FUNCTIONS Name Bit Buffer Type Function RC0/AD0 bit0 TTL Input/output or system bus address/data pin. RC1/AD1 bit1 TTL Input/output or system bus address/data pin. RC2/AD2 bit2 TTL Input/output or system bus address/data pin. RC3/AD3 bit3 TTL Input/output or system bus address/data pin. RC4/AD4 bit4 TTL Input/output or system bus address/data pin. RC5/AD5 bit5 TTL Input/output or system bus address/data pin.
PIC17C7XX 10.4 PORTD and DDRD Registers Example 10-4 shows an instruction sequence to initialize PORTD. The Bank Select Register (BSR) must be selected to Bank 1 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection. PORTD is an 8-bit bi-directional port. The corresponding data direction register is DDRD. A '1' in DDRD configures the corresponding port pin as an input.
PIC17C7XX TABLE 10-7: PORTD FUNCTIONS Name Bit Buffer Type RD0/AD8 bit0 TTL Function Input/output or system bus address/data pin. RD1/AD9 bit1 TTL Input/output or system bus address/data pin. RD2/AD10 bit2 TTL Input/output or system bus address/data pin. RD3/AD11 bit3 TTL Input/output or system bus address/data pin. RD4/AD12 bit4 TTL Input/output or system bus address/data pin. RD5/AD13 bit5 TTL Input/output or system bus address/data pin.
PIC17C7XX 10.5 PORTE and DDRE Register PORTE is a 4-bit bi-directional port. The corresponding data direction register is DDRE. A '1' in DDRE configures the corresponding port pin as an input. A '0' in the DDRE register configures the corresponding port pin as an output. Reading PORTE reads the status of the pins, whereas writing to PORTE will write to the port latch. PORTE is multiplexed with the system bus.
PIC17C7XX FIGURE 10-12: BLOCK DIAGRAM OF RE3/CAP4 PORT PIN Peripheral In D Data Bus Q EN EN VDD RD_PORTE P Q Port Data D N WR_PORTE CK Q RD_DDRE D Q WR_DDRE CK S Q Note: I/O pin has protection diodes to VDD and VSS. TABLE 10-9: PORTE FUNCTIONS Name Bit Buffer Type Function RE0/ALE bit0 TTL Input/output or system bus Address Latch Enable (ALE) control pin. RE1/OE bit1 TTL Input/output or system bus Output Enable (OE) control pin.
PIC17C7XX 10.6 PORTF and DDRF Registers Example 10-6 shows an instruction sequence to initialize PORTF. The Bank Select Register (BSR) must be selected to Bank 5 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection. PORTF is an 8-bit wide bi-directional port. The corresponding data direction register is DDRF. A '1' in DDRF configures the corresponding port pin as an input.
PIC17C7XX TABLE 10-11: PORTF FUNCTIONS Name Bit Buffer Type Function RF0/AN4 bit0 ST Input/output or analog input 4. RF1/AN5 bit1 ST Input/output or analog input 5. RF2/AN6 bit2 ST Input/output or analog input 6. RF3/AN7 bit3 ST Input/output or analog input 7. RF4/AN8 bit4 ST Input/output or analog input 8. RF5/AN9 bit5 ST Input/output or analog input 9. RF6/AN10 bit6 ST Input/output or analog input 10. RF7/AN11 bit7 ST Input/output or analog input 11.
PIC17C7XX 10.7 PORTG and DDRG Registers Example 10-7 shows the instruction sequence to initialize PORTG. The Bank Select Register (BSR) must be selected to Bank 5 for the port to be initialized. The following example uses the MOVLB instruction to load the BSR register for bank selection. PORTG is an 8-bit wide, bi-directional port. The corresponding data direction register is DDRG. A '1' in DDRG configures the corresponding port pin as an input.
PIC17C7XX FIGURE 10-15: RG4 BLOCK DIAGRAM Peripheral Data In Data Bus Q D EN EN RD_PORTG D VDD WR_PORTG CK Q P RD_DDRG D Q N Q WR_DDRG CK Note: I/O pins have protection diodes to VDD and VSS. FIGURE 10-16: RG7:RG5 BLOCK DIAGRAM Peripheral Data In D Data Bus Q NEN RD_PORTG VDD 1 P Port Data D Q Q WR_PORTG CK 0 D Q N Q CK R RD_DDRG WR_DDRG OUTPUT OUTPUT ENABLE Note: I/O pins have protection diodes to VDD and VSS. 1998-2013 Microchip Technology Inc.
PIC17C7XX TABLE 10-13: PORTG FUNCTIONS Name Bit Buffer Type bit0 ST Input/output or analog input 3. RG1/AN2 bit1 ST Input/output or analog input 2. RG2/AN1/VREF- bit2 ST Input/output or analog input 1 or the ground reference voltage. RG3/AN0/VREF+ bit3 ST Input/output or analog input 0 or the positive reference voltage. RG4/CAP3 bit4 ST Input/output or the Capture3 input pin. RG5/PWM3 bit5 ST Input/output or the PWM3 output pin.
PIC17C7XX 10.8 EXAMPLE 10-8: PORTH and DDRH Registers (PIC17C76X only) MOVLB MOVLW MOVPF CLRF PORTH is an 8-bit wide, bi-directional port. The corresponding data direction register is DDRH. A '1' in DDRH configures the corresponding port pin as an input. A '0' in the DDRH register configures the corresponding port pin as an output. Reading PORTH reads the status of the pins, whereas writing to PORTH will write to the respective port latch.
PIC17C7XX FIGURE 10-18: RH3:RH0 BLOCK DIAGRAM Data Bus Q D EN EN RD_PORTH D VDD Q RD_DDRH D Q N WR_PORTH CK Q P WR_DDRH CK Note: I/O pins have protection diodes to VDD and VSS. TABLE 10-15: PORTH FUNCTIONS Bit Buffer Type RH0 Name bit0 ST Input/output. Function RH1 bit1 ST Input/output. RH2 bit2 ST Input/output. RH3 bit3 ST Input/output. RH4/AN12 bit4 ST Input/output or analog input 12. RH5/AN13 bit5 ST Input/output or analog input 13.
PIC17C7XX 10.9 EXAMPLE 10-9: PORTJ and DDRJ Registers (PIC17C76X only) MOVLB CLRF PORTJ is an 8-bit wide, bi-directional port. The corresponding data direction register is DDRJ. A '1' in DDRJ configures the corresponding port pin as an input. A '0' in the DDRJ register configures the corresponding port pin as an output. Reading PORTJ reads the status of the pins, whereas writing to PORTJ will write to the respective port latch. PORTJ is a general purpose I/O port.
PIC17C7XX TABLE 10-17: PORTJ FUNCTIONS Name Bit Buffer Type Function RJ0 bit0 ST Input/output RJ1 bit1 ST Input/output RJ2 bit2 ST Input/output RJ3 bit3 ST Input/output RJ4 bit4 ST Input/output RJ5 bit5 ST Input/output RJ6 bit6 ST Input/output RJ7 bit7 ST Input/output Legend: ST = Schmitt Trigger input TABLE 10-18: REGISTERS/BITS ASSOCIATED WITH PORTJ Address Name 12h, Bank 8 DDRJ 13h, Bank 8 PORTJ Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RJ2 RJ1 R
PIC17C7XX 10.10 I/O Programming Considerations 10.10.1 EXAMPLE 10-10: BI-DIRECTIONAL I/O PORTS Any instruction which writes, operates internally as a read, followed by a write operation. For example, the BCF and BSF instructions read the register into the CPU, execute the bit operation and write the result back to the register. Caution must be used when these instructions are applied to a port with both inputs and outputs defined.
PIC17C7XX 10.10.2 SUCCESSIVE OPERATIONS ON I/O PORTS Figure 10-21 shows the I/O model which causes this situation. As the effective capacitance (C) becomes larger, the rise/fall time of the I/O pin increases. As the device frequency increases, or the effective capacitance increases, the possibility of this subsequent PORTx read-modify-write instruction issue increases. This effective capacitance includes the effects of the board traces.
PIC17C7XX 11.0 OVERVIEW OF TIMER RESOURCES The PIC17C7XX has four timer modules. Each module can generate an interrupt to indicate that an event has occurred. These timers are called: • Timer0 - 16-bit timer with programmable 8-bit prescaler • Timer1 - 8-bit timer • Timer2 - 8-bit timer • Timer3 - 16-bit timer For enhanced time base functionality, four input Captures and three Pulse Width Modulation (PWM) outputs are possible.
PIC17C7XX NOTES: DS30289C-page 96 1998-2013 Microchip Technology Inc.
PIC17C7XX 12.0 TIMER0 The Timer0 module consists of a 16-bit timer/counter, TMR0. The high byte is register TMR0H and the low byte is register TMR0L. A software programmable 8-bit prescaler makes Timer0 an effective 24-bit overflow timer. The clock source is software programmable as either the internal instruction clock, or an external clock on the RA1/T0CKI pin. The control bits for this module are in register T0STA (Figure 12-1).
PIC17C7XX 12.1 Timer0 Operation 12.2 When the T0CS (T0STA<5>) bit is set, TMR0 increments on the internal clock. When T0CS is clear, TMR0 increments on the external clock (RA1/T0CKI pin). The external clock edge can be selected in software. When the T0SE (T0STA<6>) bit is set, the timer will increment on the rising edge of the RA1/T0CKI pin. When T0SE is clear, the timer will increment on the falling edge of the RA1/T0CKI pin. The prescaler can be programmed to introduce a prescale of 1:1 to 1:256.
PIC17C7XX 12.3 Read/Write Consideration for TMR0 Although TMR0 is a 16-bit timer/counter, only 8-bits at a time can be read or written during a single instruction cycle. Care must be taken during any read or write. 12.3.1 READING 16-BIT VALUE The problem in reading the entire 16-bit value is that after reading the low (or high) byte, its value may change from FFh to 00h. Example 12-1 shows a 16-bit read. To ensure a proper read, interrupts must be disabled during this routine.
PIC17C7XX FIGURE 12-4: TMR0 READ/WRITE IN TIMER MODE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 AD15:AD0 ALE WR_TRM0L WR_TMR0H RD_TMR0L TMR0L Instruction Fetched Instruction Executed 12 12 TMR0H FE 56 FF MOVFP MOVFP DATAL,TMR0L DATAH,TMR0H Write TMR0L Write TMR0H Previously Fetched Instruction AB 13 57 MOVPF TMR0L,W Read TMR0L MOVFP MOVFP DATAL,TMR0L DATAH,TMR0H Write TMR0L Write TMR0H MOVPF TMR0L,W Read TMR0L 58 MOVPF TMR0L,W Read TMR0L MOVPF TMR0L,W Read T
PIC17C7XX 13.0 TIMER1, TIMER2, TIMER3, PWMS AND CAPTURES Six other registers comprise the Capture2, Capture3, and Capture4 registers (CA2H:CA2L, CA3H:CA3L, and CA4H:CA4L). The PIC17C7XX has a wealth of timers and time based functions to ease the implementation of control applications. These time base functions include three PWM outputs and four Capture inputs.
PIC17C7XX REGISTER 13-2: TCON2 REGISTER (ADDRESS: 17h, BANK 3) R-0 CA2OVF R-0 CA1OVF R/W-0 R/W-0 PWM2ON PWM1ON R/W-0 CA1/PR3 R/W-0 TMR3ON R/W-0 R/W-0 TMR2ON TMR1ON bit 7 bit 0 bit 7 CA2OVF: Capture2 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair (CA2H:CA2L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow).
PIC17C7XX REGISTER 13-3: TCON3 REGISTER (ADDRESS: 16h, BANK 7) U-0 — R-0 CA4OVF R-0 CA3OVF R/W-0 CA4ED1 R/W-0 CA4ED0 R/W-0 CA3ED1 R/W-0 R/W-0 CA3ED0 PWM3ON bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6 CA4OVF: Capture4 Overflow Status bit This bit indicates that the capture value had not been read from the capture register pair (CA4H:CA4L) before the next capture event occurred. The capture register retains the oldest unread capture value (last capture before overflow).
PIC17C7XX 13.1 13.1.1 Timer1 and Timer2 TIMER1, TIMER2 IN 8-BIT MODE Both Timer1 and Timer2 will operate in 8-bit mode when the T16 bit is clear. These two timers can be independently configured to increment from the internal instruction cycle clock (TCY), or from an external clock source on the RB4/TCLK12 pin. The timer clock source is configured by the TMRxCS bit (x = 1 for Timer1, or = 2 for Timer2).
PIC17C7XX 13.1.2 TIMER1 AND TIMER2 IN 16-BIT MODE 13.1.2.1 To select 16-bit mode, set the T16 bit. In this mode, TMR2 and TMR1 are concatenated to form a 16-bit timer (TMR2:TMR1). The 16-bit timer increments until it matches the 16-bit period register (PR2:PR1). On the following timer clock, the timer value is reset to 0h, and the TMR1IF bit is set.
PIC17C7XX TABLE 13-3: Address SUMMARY OF TIMER1, TIMER2 AND TIMER3 REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CA2ED0 CA1ED1 CA1ED0 T16 Bit 2 Bit 1 Bit 0 Value on POR, BOR MCLR, WDT 16h, Bank 3 TCON1 CA2ED1 TMR3CS TMR2CS TMR1CS 0000 0000 0000 0000 17h, Bank 3 TCON2 CA2OVF CA1OVF PWM2ON PWM1ON CA1/PR3 TMR3ON TMR2ON TMR1ON 0000 0000 0000 0000 16h, Bank 7 TCON3 PWM3ON -000 0000 -000 0000 10h, Bank 2 TMR1 Timer1’s Register xxxx xxxx uuuu uuuu 11h, Bank 2 TMR2 Timer2’s R
PIC17C7XX 13.1.3 USING PULSE WIDTH MODULATION (PWM) OUTPUTS WITH TIMER1 AND TIMER2 The user needs to set the PWM1ON bit (TCON2<4>) to enable the PWM1 output. When the PWM1ON bit is set, the RB2/PWM1 pin is configured as PWM1 output and forced as an output, irrespective of the data direction bit (DDRB<2>). When the PWM1ON bit is clear, the pin behaves as a port pin and its direction is controlled by its data direction bit (DDRB<2>).
PIC17C7XX 13.1.3.1 PWM Periods The period of the PWM1 output is determined by Timer1 and its period register (PR1). The period of the PWM2 and PWM3 outputs can be individually software configured to use either Timer1 or Timer2 as the timebase. For PWM2, when TM2PW2 bit (PW2DCL<5>) is clear, the time base is determined by TMR1 and PR1 and when TM2PW2 is set, the time base is determined by Timer2 and PR2.
PIC17C7XX 13.1.3.3 External Clock Source 13.1.3.4 The PWMs will operate, regardless of the clock source of the timer. The use of an external clock has ramifications that must be understood. Because the external TCLK12 input is synchronized internally (sampled once per instruction cycle), the time TCLK12 changes to the time the timer increments, will vary by as much as 1TCY (one instruction cycle). This will cause jitter in the duty cycle as well as the period of the PWM output.
PIC17C7XX 13.2 Timer3 (RB0/CAP1, RB1/CAP2, RG4/CAP3, and RE3/CAP4), one for each capture register pair. The capture pins are multiplexed with the I/O pins. An event can be: Timer3 is a 16-bit timer consisting of the TMR3H and TMR3L registers. TMR3H is the high byte of the timer and TMR3L is the low byte. This timer has an associated 16-bit period register (PR3H/CA1H:PR3L/CA1L). This period register can be software configured to be a another 16-bit capture register.
PIC17C7XX This mode (3 Capture, 1 Period) is selected if control bit CA1/PR3 is clear. In this mode, the Capture1 register, consisting of high byte (PR3H/CA1H) and low byte (PR3L/CA1L), is configured as the period control register for TMR3. Capture1 is disabled in this mode and the corresponding interrupt bit, CA1IF, is never set. TMR3 increments until it equals the value in the period register and then resets to 0000h on the next timer clock. All other Captures are active in this mode. 13.2.1.
PIC17C7XX 13.2.2 FOUR CAPTURE MODE Registers PR3H/CA1H and PR3L/CA1L make a 16-bit capture register (Capture1). It captures events on pin RB0/CAP1. Capture mode is configured by the CA1ED1 and CA1ED0 bits. Capture1 Interrupt Flag bit (CA1IF) is set upon detection of the capture event. The corresponding interrupt mask bit is CA1IE. The Capture1 Overflow Status bit is CA1OVF. This mode is selected by setting bit CA1/PR3. A block diagram is shown in Figure 13-6.
PIC17C7XX 13.2.3 READING THE CAPTURE REGISTERS order) of the Capture register, the master overflow bit is transferred to the slave overflow bit (CAxOVF) and then the master bit is reset. The user can then read TCONx to determine the value of CAxOVF. The Capture overflow status flag bits are double buffered. The master bit is set if one captured word is already residing in the Capture register and another “event” has occurred on the CAPx pin.
PIC17C7XX 13.2.4 EXTERNAL CLOCK INPUT FOR TIMER3 13.2.5 Since Timer3 is a 16-bit timer and only 8-bits at a time can be read or written, care should be taken when reading or writing while the timer is running. The best method is to stop the timer, perform any read or write operation and then restart Timer3 (using the TMR3ON bit). However, if it is necessary to keep Timer3 freerunning, care must be taken. For writing to the 16-bit TMR3, Example 13-2 may be used.
PIC17C7XX FIGURE 13-8: TIMER1, TIMER2 AND TIMER3 OPERATION (IN TIMER MODE) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1Q2 Q3 Q4 AD15:AD0 ALE Instruction Fetched TMR1 MOVF MOVWF MOVF TMR1, W TMR1 TMR1, W Write TMR1 Read TMR1 Read TMR1 04h 05h 03h MOVLB 3 04h BSF TCON2, 0 Stop TMR1 05h NOP 06h BCF TCON2, 0 Start TMR1 NOP 07h NOP NOP 08h NOP 00h PR1 TMR1ON WR_TMR1 WR_TCON2 TMR1IF RD_TMR1 TMR1 Reads 03h 1998-201
PIC17C7XX NOTES: DS30289C-page 116 1998-2013 Microchip Technology Inc.
PIC17C7XX 14.0 UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) MODULES TABLE 14-1: Generic Name RCSTA TXSTA SPBRG RCREG TXREG Each USART module is a serial I/O module. There are two USART modules that are available on the PIC17C7XX. They are specified as USART1 and USART2. The description of the operation of these modules is generic in regard to the register names and pin names used.
PIC17C7XX The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices such as A/D or D/A integrated circuits, Serial EEPROMs etc. The USART can be configured in the following modes: The SPEN (RCSTA<7>) bit has to be set in order to configure the I/O pins as the Serial Communication Interface (USART).
PIC17C7XX FIGURE 14-1: USART TRANSMIT Sync Master/Slave 4 BRG Sync/Async Sync/Async TSR Sync/Async CK/TX 16 Start 0 1 7 8 Stop Clock Load TXEN/ Write to TXREG DT TXREG 0 1 7 8 Bit Count Interrupt TXSTA<0> Data Bus FIGURE 14-2: OSC USART RECEIVE BRG Interrupt 4 Master/Slave Sync CK TXIE Buffer Logic Sync/Async Async/Sync Enable Bit Count 16 START Detect SPEN RX Buffer Logic RCIE Majority Detect RSR Clock Data SREN/ CREN/ Start_Bit MSb LSb Stop 8 7
PIC17C7XX 14.1 EXAMPLE 14-1: USART Baud Rate Generator (BRG) Desired Baud Rate = FOSC / (64 (X + 1)) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. Table 14-2 shows the formula for computation of the baud rate for different USART modes. These only apply when the USART is in Synchronous Master mode (internal clock) and Asynchronous mode.
PIC17C7XX TABLE 14-4: BAUD RATE (K) BAUD RATES FOR SYNCHRONOUS MODE FOSC = 33 MHz KBAUD FOSC = 25 MHz FOSC = 20 MHz FOSC = 16 MHz SPBRG SPBRG SPBRG SPBRG VALUE VALUE VALUE VALUE %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) 0.3 NA — — NA — — NA — — NA — — 1.2 NA — — NA — — NA — — NA — — 2.4 NA — — NA — — NA — — NA — — 9.6 NA — — NA — — NA — — NA — — 19.2 NA — — NA — — 19.53 +1.73 255 19.23 +0.
PIC17C7XX TABLE 14-5: BAUD RATE (K) BAUD RATES FOR ASYNCHRONOUS MODE FOSC = 33 MHz KBAUD FOSC = 25 MHz FOSC = 20 MHz FOSC = 16 MHz SPBRG SPBRG SPBRG SPBRG VALUE VALUE VALUE VALUE %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) KBAUD %ERROR (DECIMAL) 0.3 NA — — NA — — NA — — NA — — 1.2 NA — — NA — — 1.221 +1.73 255 1.202 +0.16 207 2.4 2.398 -0.07 214 2.396 0.14 162 2.404 +0.16 129 2.404 +0.16 103 9.6 9.548 -0.54 53 9.53 -0.76 40 9.469 -1.
PIC17C7XX 14.2 USART Asynchronous Mode In this mode, the USART uses standard nonreturn-tozero (NRZ) format (one START bit, eight or nine data bits, and one STOP bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART’s transmitter and receiver are functionally independent but use the same data format and baud rate. The baud rate generator produces a clock x64 of the bit shift rate.
PIC17C7XX FIGURE 14-4: ASYNCHRONOUS MASTER TRANSMISSION (BACK TO BACK) Write to TXREG Word 1 BRG output (shift clock) TX (TX/CK pin) Word 2 START Bit Bit 0 Bit 1 Word 1 TXIF bit Bit 7/8 Bit 0 Word 2 Word 1 Transmit Shift Reg. TRMT bit START Bit STOP Bit Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions.
PIC17C7XX 14.2.2 USART ASYNCHRONOUS RECEIVER ting the receive logic (CREN is set). If the OERR bit is set, transfers from the RSR to RCREG are inhibited, so it is essential to clear the OERR bit if it is set. The framing error bit FERR (RCSTA<2>) is set if a STOP bit is not detected. The receiver block diagram is shown in Figure 14-2. The data comes in the RX/DT pin and drives the data recovery block.
PIC17C7XX 7. Steps to follow when setting up an Asynchronous Reception: 1. 2. 3. 4. 5. 6. Initialize the SPBRG register for the appropriate baud rate. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. If interrupts are desired, then set the RCIE bit. If 9-bit reception is desired, then set the RX9 bit. Enable the reception by setting the CREN bit. The RCIF bit will be set when reception completes and an interrupt will be generated if the RCIE bit was set.
PIC17C7XX 14.3 USART Synchronous Master Mode In Master Synchronous mode, the data is transmitted in a half-duplex manner; i.e., transmission and reception do not occur at the same time: when transmitting data, the reception is inhibited and vice versa. The synchronous mode is entered by setting the SYNC (TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit is set in order to configure the I/O pins to CK (clock) and DT (data) lines, respectively.
PIC17C7XX TABLE 14-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR MCLR, WDT 16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010 17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000 13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u 16h, Bank 0 TXREG1 TX7 TX6 TX5 TX4 TX3 TX2
PIC17C7XX 14.3.2 USART SYNCHRONOUS MASTER RECEPTION Steps to follow when setting up a Synchronous Master Reception: 1. Once Synchronous mode is selected, reception is enabled by setting either the SREN (RCSTA<5>) bit or the CREN (RCSTA<4>) bit. Data is sampled on the RX/ DT pin on the falling edge of the clock. If SREN is set, then only a single word is received. If CREN is set, the reception is continuous until CREN is reset. If both bits are set, then CREN takes precedence.
PIC17C7XX TABLE 14-9: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR MCLR, WDT u000 0010 16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000 13h, Bank 0 RCSTA1 SPEN RX9 CREN — FERR OERR RX9D 0000 -00x 0000 -00u SREN 14h, Bank 0 RCREG1 RX7 RX6 RX5 RX4 RX3 RX2 R
PIC17C7XX 14.4 USART Synchronous Slave Mode The Synchronous Slave mode differs from the Master mode, in the fact that the shift clock is supplied externally at the TX/CK pin (instead of being supplied internally in the Master mode). This allows the device to transfer or receive data in the SLEEP mode. The Slave mode is entered by clearing the CSRC (TXSTA<7>) bit. 14.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the SYNC Master and Slave modes are identical except in the case of the SLEEP mode.
PIC17C7XX TABLE 14-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR MCLR, WDT 16h, Bank 1 PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF x000 0010 u000 0010 17h, Bank 1 PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE 0000 0000 0000 0000 13h, Bank 0 RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00u 15h, Bank 0 TXSTA1 CSRC TX9 TXEN SYNC — —
PIC17C7XX 15.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC17C7XX REGISTER 15-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS: 13h, BANK 6) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 7 bit 0 SMP: Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate co
PIC17C7XX REGISTER 15-2: SSPCON1: SYNC SERIAL PORT CONTROL REGISTER1 (ADDRESS 11h, BANK 6) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be c
PIC17C7XX REGISTER 15-3: SSPCON2: SYNC SERIAL PORT CONTROL REGISTER2 (ADDRESS 12h, BANK 6) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (in I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (in I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not receive
PIC17C7XX 15.1 SPI Mode FIGURE 15-4: The SPI mode allows 8-bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read • Serial Data Out (SDO) • Serial Data In (SDI) • Serial Clock (SCK) Write SSPBUF reg Additionally, a fourth pin may be used when in a Slave mode of operation: SSPSR reg • Slave Select (SS) SDI 15.1.
PIC17C7XX When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. Buffer full bit, BF (SSPSTAT<0>), indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, bit BF is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally the MSSP interrupt is used to determine when the transmission/reception has completed.
PIC17C7XX 15.1.4 MASTER MODE Figure 15-6, Figure 15-8 and Figure 15-9, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 15-5) is to broadcast data by the software protocol. • • • • In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to.
PIC17C7XX 15.1.5 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the interrupt flag bit SSPIF (PIR2<7>) is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. the SDO pin is driven.
PIC17C7XX FIGURE 15-8: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit0 bit7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 cycle after Q2 SSPSR to SSPBUF FIGURE 15-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS not optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit7 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit
PIC17C7XX 15.1.7 SLEEP OPERATION shifted into the SPI transmit/receive shift register. When all 8-bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device from SLEEP. In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/ receive data. 15.1.
PIC17C7XX 15.2 MSSP I2 C Operation I2C MASTER MODE BLOCK DIAGRAM FIGURE 15-11: The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
PIC17C7XX The SSPSTAT register gives the status of the data transfer. This information includes detection of a START or STOP bit, specifies if the received byte was data or address if the next byte is the completion of 10-bit address and if this will be a read or write data transfer. The SSPBUF is the register to which transfer data is written to or read from. The SSPSR register shifts the data in or out of the device. In receive operations, the SSPBUF and SSPSR create a doubled buffered receiver.
PIC17C7XX 15.2.1.1 Addressing 5. Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC17C7XX 15.2.1.3 Slave Transmission An SSP interrupt is generated for each data transfer byte. The SSPIF flag bit must be cleared in software, and the SSPSTAT register is used to determine the status of the byte transfer. The SSPIF flag bit is set on the falling edge of the ninth clock pulse. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register.
1998-2013 Microchip Technology Inc. 2 UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 S SCL 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK Receive First Byte of Address R/W = 0 1 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated.
DS30289C-page 148 UA (SSPSTAT<1>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 2 1 3 1 5 0 6 A9 7 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 4 1 9 ACK R/W = 0 1 2 3 A5 4 A4 Cleared in software A6 5 A3 6 A2 7 A1 8 A0 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC17C7XX 15.2.2 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF flag is set. The addressing procedure for the I2C bus is such that the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices.
PIC17C7XX 15.2.3 SLEEP OPERATION 15.2.4 While in SLEEP mode, the I2C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the SSP interrupt is enabled). TABLE 15-3: Address EFFECTS OF A RESET A RESET disables the SSP module and terminates the current transfer.
PIC17C7XX 15.2.5 MASTER MODE The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle, with both the S and P bits clear.
PIC17C7XX 15.2.6 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when bit P (SSPSTAT<4>) is set, or the bus is idle, with both the S and P bits clear. When the bus is busy, enabling the SSP interrupt will generate the interrupt when the STOP condition occurs.
PIC17C7XX A typical transmit sequence would go as follows: 15.2.8 a) In I2C Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 15-18). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY), on the Q2 and Q4 clock.
PIC17C7XX 15.2.9 I2C MASTER MODE START CONDITION TIMING 15.2.9.1 If the user writes the SSPBUF when a START sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a START condition, the user sets the START condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC17C7XX FIGURE 15-21: START CONDITION FLOW CHART SSPEN = 1, SSPCON1<3:0> = 1000 Idle Mode SEN (SSPCON2<0> = 1) Bus Collision Detected, Set BCLIF, Release SCL, Clear SEN No SDA = 1? SCL = 1? Yes Load BRG with SSPADD<6:0> No Yes No No SCL= 0? SDA = 0? Yes BRG Rollover? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0>, Set S bit. No SCL = 0? Yes No BRG Rollover? Yes Reset BRG Force SCL = 0, START Condition Done, Clear SEN and set SSPIF 1998-2013 Microchip Technology Inc.
PIC17C7XX 15.2.10 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode), or eight bits of data (7-bit mode).
PIC17C7XX FIGURE 15-23: REPEATED START CONDITION FLOW CHART (PAGE 1) Start Idle Mode, SSPEN = 1, SSPCON1<3:0> = 1000 B RSEN = 1 Force SCL = 0 No SCL = 0? Yes Release SDA, Load BRG with SSPADD<6:0> BRG Rollover? No Yes Release SCL (Clock Arbitration) SCL = 1? No Yes Bus Collision, Set BCLIF, Release SDA, Clear RSEN No SDA = 1? Yes Load BRG with SSPADD<6:0> C 1998-2013 Microchip Technology Inc.
PIC17C7XX FIGURE 15-24: REPEATED START CONDITION FLOW CHART (PAGE 2) B C A Yes No No No SDA = 0? SCL = 1? Yes BRG Rollover? Yes Reset BRG Force SDA = 0, Load BRG with SSPADD<6:0> Set S No SCL = '0'? Yes Reset BRG DS30289C-page 158 No BRG Rollover? Yes Force SCL = 0, Repeated Start condition done, Clear RSEN, Set SSPIF. 1998-2013 Microchip Technology Inc.
PIC17C7XX 15.2.11 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address, or either half of a 10-bit address, is accomplished by simply writing a value to SSPBUF register. This action will set the buffer full flag (BF) and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time spec).
PIC17C7XX FIGURE 15-25: MASTER TRANSMIT FLOW CHART Idle Mode Write SSPBUF Num_Clocks = 0, BF = 1 Force SCL = 0 Release SDA so Slave can drive ACK, Force BF = 0 Yes Num_Clocks = 8? No Load BRG with SSPADD<6:0>, start BRG count Load BRG with SSPADD<6:0>, Start BRG Count, SDA = Current Data bit BRG Rollover? No BRG Rollover? No Yes Yes Force SCL = 1, Stop BRG Stop BRG, Force SCL = 1 (Clock Arbitration) SCL = 1? (Clock Arbitration) No SCL = 1? No Yes Yes SDA = Data bit? Read SDA and plac
1998-2013 Microchip Technology Inc. S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in Software 2 6 7 8 9 D7 1 SCL held low while CPU Responds to SSPIF After START Condition SEN Cleared by Hardware.
PIC17C7XX 15.2.12 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the receive enable bit, RCEN (SSPCON2<3>). Note: The SSP Module must be in an IDLE STATE before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting and on each rollover, the state of the SCL pin changes (high to low/ low to high) and data is shifted into the SSPSR.
PIC17C7XX FIGURE 15-27: MASTER RECEIVER FLOW CHART Idle Mode RCEN = 1 Num_Clocks = 0, Release SDA Force SCL=0, Load BRG w/ SSPADD<6:0>, Start Count BRG Rollover? No Yes Release SCL (Clock Arbitration) SCL = 1? No Yes Sample SDA, Shift Data into SSPSR Load BRG with SSPADD<6:0>, Start Count. BRG Rollover? No Yes SCL = 0? No Yes Num_Clocks = Num_Clocks + 1 No Num_Clocks = 8? Yes Force SCL = 0, Set SSPIF, Set BF. Move Contents of SSPSR into SSPBUF, Clear RCEN.
DS30289C-page 164 S ACKEN SSPOV BF (SSPSTAT<0>) SDA = 0, SCL = 1 while CPU Responds to SSPIF SSPIF SCL SDA 2 1 A4 4 A5 3 5 A3 A2 6 Cleared in Software A6 Transmit Address to Slave A7 7 A1 8 9 R/W = 1 ACK ACK from Slave 2 D6 3 D5 5 D3 6 D2 7 D1 8 D0 9 ACK 2 D6 3 D5 4 D4 5 D3 6 D2 Receiving Data from Slave 7 D1 Cleared in Software Set SSPIF Interrupt at End of Acknowledge Sequence Cleared in Software Set SSPIF at End of Receive 9 ACK is Not Sent ACK
PIC17C7XX 15.2.13 ACKNOWLEDGE SEQUENCE TIMING 15.2.13.1 If the user writes the SSPBUF when an acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). An acknowledge sequence is enabled by setting the acknowledge sequence enable bit, ACKEN (SSPCON2<4>). When this bit is set, the SCL pin is pulled low and the contents of the acknowledge data bit is presented on the SDA pin.
PIC17C7XX FIGURE 15-30: ACKNOWLEDGE FLOW CHART Idle Mode Set ACKEN Force SCL = 0 BRG Rollover? Yes No No SCL = 0? Yes Yes Drive ACKDT bit (SSPCON2<5>) onto SDA pin, Load BRG with SSPADD<6:0>, Start Count. SCL = 0? Reset BRG Force SCL = 0, Clear ACKEN Set SSPIF No No ACKDT = 1? Yes No BRG Rollover? Yes Yes Force SCL = 1 SDA = 1? No Bus Collision Detected, Set BCLIF, Release SCL, Clear ACKEN No SCL = 1? (Clock Arbitration) Yes Load BRG with SSPADD <6:0>, Start Count.
PIC17C7XX 15.2.14 STOP CONDITION TIMING 15.2.14.1 WCOL Status Flag If the user writes the SSPBUF when a STOP sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit PEN (SSPCON2<2>). At the end of a receive/ transmit the SCL line is held low after the falling edge of the ninth clock.
PIC17C7XX FIGURE 15-32: STOP CONDITION FLOW CHART Idle Mode, SSPEN = 1, SSPCON1<3:0> = 1000 PEN = 1 Start BRG Force SDA = 0 SCL Doesn’t Change BRG Rollover? No SDA = 0? No Yes Release SDA, Start BRG Yes Start BRG BRG Rollover? BRG Rollover? No No Yes No P bit Set? Yes De-assert SCL, SCL = 1 Yes (Clock Arbitration) SCL = 1? Bus Collision Detected, Set BCLIF, Clear PEN No SDA going from 0 to 1 while SCL = 1 Set SSPIF, STOP Condition done, PEN cleared Yes DS30289C-page 168 1998-2013 Mic
PIC17C7XX 15.2.15 CLOCK ARBITRATION 15.2.16 Clock arbitration occurs when the master, during any receive, transmit, or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC17C7XX 15.2.18 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA, by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place.
PIC17C7XX 15.2.18.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) SDA or SCL are sampled low at the beginning of the START condition (Figure 15-35). SCL is sampled low before SDA is asserted low (Figure 15-36). b) During a START condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-37).
PIC17C7XX FIGURE 15-36: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START sequence if SDA = 1, SCL = 1. SCL SCL = 0 before SDA = 0, Bus collision occurs, Set BCLIF. SEN SCL = 0 before BRG time-out, Bus collision occurs, Set BCLIF. BCLIF Interrupts cleared in software. S '0' '0' SSPIF '0' '0' FIGURE 15-37: BRG RESET DUE TO SDA COLLISION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG SDA TBRG SDA pulled low by other master.
PIC17C7XX 15.2.18.2 Bus Collision During a Repeated Start Condition reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. During a Repeated Start condition, a bus collision occurs if: a) b) If, however, SCL goes from high to low before the BRG times out and SDA has not already been asserted, then a bus collision occurs.
PIC17C7XX 15.2.18.3 Bus Collision During a STOP Condition The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to ‘0’. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0'.
PIC17C7XX 15.3 Connection Considerations for I2C Bus For standard mode I2C bus devices, the values of resistors Rp Rs in Figure 15-42 depends on the following parameters: example, with a supply voltage of VDD = 5V +10% and VOL max = 0.4V at 3 mA, Rp min = (5.5-0.4)/0.003 = 1.7 k VDD as a function of Rp is shown in Figure 1542. The desired noise margin of 0.1 VDD for the low level, limits the maximum value of Rs. Series resistors are optional and used to improve ESD susceptibility.
PIC17C7XX 15.4 Example Program Example 15-2 shows MPLAB® C17 ’C’ code for using the I2C module in Master mode to communicate with a 24LC01B serial EEPROM. This example uses the PIC® MCU ‘C’ libraries included with MPLAB C17. EXAMPLE 15-2: INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB C17) // Include necessary header files #include // Processor header file #include // Delay routines header file #include // Standard Library header file #include
PIC17C7XX EXAMPLE 15-2: INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB C17) // Writes the byte data to 24LC01B at the specified address void ByteWrite(static unsigned char address, static unsigned char data) { StartI2C(); // Send start bit IdleI2C(); // Wait for idle condition WriteI2C(CONTROL); // Send control byte IdleI2C(); // Wait for idle condition if (!SSPCON2bits.ACKSTAT) // If 24LC01B ACKs { WriteI2C(address); // Send control byte IdleI2C(); // Wait for idle condition if (!SSPCON2bits.
PIC17C7XX EXAMPLE 15-2: INTERFACING TO A 24LC01B SERIAL EEPROM (USING MPLAB C17) void ACKPoll(void) { StartI2C(); // Send start bit IdleI2C(); // Wait for idle condition WriteI2C(CONTROL); // Send control byte IdleI2C(); // Wait for idle condition // Poll the ACK bit coming from the 24LC01B // Loop as long as the 24LC01B NACKs while (SSPCON2bits.
PIC17C7XX 16.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The analog-to-digital (A/D) converter module has twelve analog inputs for the PIC17C75X devices and sixteen for the PIC17C76X devices. The analog input charges a sample and hold capacitor. The output of the sample and hold capacitor is the input into the converter. The converter then generates a digital result of this analog level via successive approximation.
PIC17C7XX REGISTER 16-2: ADCON1 REGISTER (ADDRESS 15h, BANK 5) R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS1 ADCS0 ADFM — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7-6 ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/8 01 = FOSC/32 10 = FOSC/64 11 = FRC (clock derived from an internal RC oscillator) bit 5 ADFM: A/D Result Format Select 1 = Right justified. 6 Most Significant bits of ADRESH are read as ’0’. 0 = Left justified.
PIC17C7XX The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared and A/D interrupt flag bit, ADIF is set. The block diagrams of the A/D module are shown in Figure 16-1. 2. 3. 4. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC17C7XX Figure 16-2 shows the conversion sequence and the terms that are used. Acquisition time is the time that the A/D module’s holding capacitor is connected to the external voltage level. Then, there is the conversion time of 12 TAD, which is started when the GO bit is set. The sum of these two times is the sampling time. There is a minimum acquisition time to ensure that the holding capacitor is charged to a level that will give the desired accuracy for the A/D conversion.
PIC17C7XX 16.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 16-3. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), Figure 16-3.
PIC17C7XX FIGURE 16-3: ANALOG INPUT MODEL VDD RS ANx CPIN 5 pF VA Sampling Switch VT = 0.6V VT = 0.
PIC17C7XX 16.2 Selecting the A/D Conversion Clock For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12TAD per 10-bit conversion. The source of the A/D conversion clock is software selected.
PIC17C7XX 16.3 Configuring Analog Port Pins The ADCON1, and DDR registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding DDR bits set (input). If the DDR bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS2:CHS0 bits and the DDR bits.
PIC17C7XX FIGURE 16-5: FLOW CHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes GO = 0? No A/D Clock = RC? Yes Start of A/D Conversion Delayed 1 Instruction Cycle Finish Conversion GO = 0, ADIF = 1 No No Device in SLEEP? Yes SLEEP Instruction? Yes Abort Conversion GO = 0, ADIF = 0 Finish Conversion GO = 0, ADIF = 1 Wait 2TAD No No Finish Conversion GO = 0, ADIF = 1 Wake-up Yes From SLEEP? SLEEP Power-down A/D Wait 2TAD Stay in SLEEP Power-down A/D Wait 2TAD
PIC17C7XX 16.4.1 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 16-6 shows the operation of the A/D result justification. The extra bits are loaded with ’0’s’.
PIC17C7XX The maximum pin leakage current is specified in the Device Data Sheet electrical specification (Table 20-2, parameter #D060). Transfer Function The transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage (VAIN) equals Analog VREF / 1024 (Figure 16-7). FIGURE 16-7: A/D TRANSFER FUNCTION 3FFh 3FEh 003h 002h 1023 LSb 000h 1023.5 LSb 001h 1022.
PIC17C7XX 16.10 References A good reference for understanding A/D converter is the "Analog-Digital Conversion Handbook" third edition, published by Prentice Hall (ISBN 0-13-03-2848-0).
PIC17C7XX 17.0 SPECIAL FEATURES OF THE CPU What sets a microcontroller apart from other processors are special circuits to deal with the needs of realtime applications. The PIC17CXXX family has a host of such features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection. These are: • Oscillator Selection (Section 4.0) • RESET (Section 5.
PIC17C7XX 17.1 Configuration Bits 17.2 The PIC17CXXX has eight configuration locations (Table 17-1). These locations can be programmed (read as '0'), or left unprogrammed (read as '1') to select various device configurations. Any write to a configuration location, regardless of the data, will program that configuration bit. A TABLWT instruction and raising the MCLR/VPP pin to the programming voltage are both required to write to program memory locations.
PIC17C7XX 17.3 17.3.2 Watchdog Timer (WDT) The Watchdog Timer’s function is to recover from software malfunction, or to reset the device while in SLEEP mode. The WDT uses an internal free running on-chip RC oscillator for its clock source. This does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin.
PIC17C7XX 17.4 Power-down Mode (SLEEP) Any RESET event will cause a device RESET. Any interrupt event is considered a continuation of program execution. The TO and PD bits in the CPUSTA register can be used to determine the cause of a device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared if WDT time-out occurred (and caused a RESET). The Power-down mode is entered by executing a SLEEP instruction.
PIC17C7XX 17.4.2 MINIMIZING CURRENT CONSUMPTION To minimize current consumption, all I/O pins should be either at VDD, or VSS, with no external circuitry drawing current from the I/O pin. I/O pins that are hi-impedance inputs should be pulled high or low externally to avoid switching currents caused by floating inputs. The T0CKI input should be at VDD or VSS. The contributions from on-chip pull-ups on PORTB should also be considered and disabled, when possible. 17.
PIC17C7XX 17.6 In-Circuit Serial Programming The PIC17C7XX group of the high-end family (PIC17CXXX) has an added feature that allows serial programming while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product.
PIC17C7XX 18.0 INSTRUCTION SET SUMMARY The PIC17CXXX instruction set consists of 58 instructions. Each instruction is a 16-bit word divided into an OPCODE and one or more operands. The opcode specifies the instruction type, while the operand(s) further specify the operation of the instruction. The PIC17CXXX instruction set can be grouped into three types: • byte-oriented • bit-oriented • literal and control operations These formats are shown in Figure 18-1.
PIC17C7XX Table 18-2 lists the instructions recognized by the MPASM assembler. Note 1: Any unused opcode is Reserved. Use of any reserved opcode may cause unexpected operation. All instruction examples use the following format to represent a hexadecimal number: The PIC17C7XX’s orthogonal instruction set allows read and write of all file registers, including special function registers.
PIC17C7XX 18.2 Q Cycle Activity The four Q cycles that make up an instruction cycle (TCY) can be generalized as: Each instruction cycle (TCY) is comprised of four Q cycles (Q1-Q4). The Q cycle is the same as the device oscillator cycle (TOSC). The Q cycles provide the timing/ designation for the Decode, Read, Process Data, Write, etc., of each instruction cycle. The following diagram shows the relationship of the Q cycles to the instruction cycle.
PIC17C7XX TABLE 18-2: PIC17CXXX INSTRUCTION SET 16-bit Opcode Mnemonic, Operands Description Cycles Status Affected MSb LSb 0000 111d ffff ffff OV,C,DC,Z Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f,d ADD WREG to f 1 ADDWFC f,d ADD WREG and Carry bit to f 1 0001 000d ffff ffff OV,C,DC,Z ANDWF AND WREG with f 1 0000 101d ffff ffff Z f,d CLRF f,s Clear f, or Clear f and Clear WREG 1 0010 100s ffff ffff None COMF f,d Complement f 1 0001 001d ffff ffff Z 3 CPF
PIC17C7XX TABLE 18-2: PIC17CXXX INSTRUCTION SET (CONTINUED) 16-bit Opcode Mnemonic, Operands Description Cycles MSb TSTFSZ f Test f, skip if 0 XORWF f,d Exclusive OR WREG with f LSb Status Affected 1 (2) 0011 0011 ffff ffff None 1 0000 110d ffff ffff Z 1 1000 1bbb ffff ffff None Notes 6,8 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f,b Bit Clear f BSF f,b Bit Set f 1 1000 0bbb ffff ffff None BTFSC f,b Bit test, skip if clear 1 (2) 1001 1bbb ffff ffff None 6,8 1 (2)
PIC17C7XX ADDLW ADD Literal to WREG ADDWF ADD WREG to f Syntax: [ label ] ADDLW Syntax: [ label ] ADDWF Operands: 0 k 255 Operands: Operation: (WREG) + k (WREG) 0 f 255 d [0,1] Status Affected: OV, C, DC, Z Operation: (WREG) + (f) (dest) Status Affected: OV, C, DC, Z Encoding: Description: 1011 0001 k kkkk kkkk The contents of WREG are added to the 8-bit literal 'k' and the result is placed in WREG.
PIC17C7XX ADDWFC ADD WREG and Carry bit to f ANDLW And Literal with WREG Syntax: [ label ] ADDWFC Syntax: [ label ] ANDLW Operands: 0 f 255 d [0,1] f,d Operation: (WREG) + (f) + C (dest) Status Affected: OV, C, DC, Z Encoding: 0001 Description: ffff ffff Add WREG, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed in data memory location 'f'. Words: 1 Cycles: 1 Operands: 0 k 255 Operation: (WREG) .
PIC17C7XX ANDWF AND WREG with f BCF Bit Clear f Syntax: [ label ] ANDWF Syntax: [ label ] BCF Operands: 0 f 255 d [0,1] Operands: 0 f 255 0b7 Operation: (WREG) .AND. (f) (dest) Operation: 0 (f) Status Affected: Z Status Affected: None Encoding: 0000 Description: 101d f,d ffff ffff Encoding: 1000 f,b 1bbb ffff ffff The contents of WREG are AND’ed with register 'f'. If 'd' is 0 the result is stored in WREG.
PIC17C7XX BSF Bit Set f BTFSC Bit Test, skip if Clear Syntax: [ label ] BSF Syntax: [ label ] BTFSC f,b Operands: 0 f 255 0b7 Operands: 0 f 255 0b7 Operation: 1 (f) Operation: skip if (f) = 0 Status Affected: None Status Affected: None Encoding: 1000 f,b 0bbb ffff Description: Bit 'b' in register 'f' is set.
PIC17C7XX BTFSS Bit Test, skip if Set BTG Bit Toggle f Syntax: [ label ] BTFSS f,b Syntax: [ label ] BTG f,b Operands: 0 f 127 0b<7 Operands: 0 f 255 0b<7 Operation: skip if (f) = 1 Operation: (f) (f) Status Affected: None Status Affected: None Encoding: Description: 1001 0bbb ffff ffff Encoding: 0011 1bbb ffff ffff If bit 'b' in register 'f' is 1, then the next instruction is skipped. Description: Bit 'b' in data memory location 'f' is inverted.
PIC17C7XX CALL Subroutine Call CLRF Clear f Syntax: [ label ] CALL k Syntax: [label] CLRF Operands: 0 k 8191 Operands: 0 f 255 Operation: PC+ 1 TOS, k PC<12:0>, k<12:8> PCLATH<4:0>; PC<15:13> PCLATH<7:5> Operation: 00h f, s [0,1] 00h dest Status Affected: None Status Affected: None Encoding: Encoding: Description: 111k kkkk kkkk kkkk Subroutine call within 8K page. First, return address (PC+1) is pushed onto the stack.
PIC17C7XX CLRWDT Clear Watchdog Timer COMF Complement f Syntax: [ label ] CLRWDT Syntax: [ label ] COMF Operands: None Operands: Operation: 00h WDT 0 WDT postscaler, 1 TO 1 PD 0 f 255 d [0,1] Operation: ( f ) (dest) Status Affected: Z Status Affected: Encoding: Description: Encoding: TO, PD 0000 0000 0000 0100 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set.
PIC17C7XX CPFSEQ Compare f with WREG, skip if f = WREG CPFSGT Syntax: [ label ] CPFSEQ Syntax: [ label ] CPFSGT Operands: 0 f 255 Operands: 0 f 255 Operation: (f) – (WREG), skip if (f) = (WREG) (unsigned comparison) Operation: (f) WREG), skip if (f) > (WREG) (unsigned comparison) Status Affected: None Status Affected: None Encoding: Description: 0011 0001 f Compare f with WREG, skip if f > WREG ffff ffff Compares the contents of data memory location 'f' to the contents o
PIC17C7XX CPFSLT Compare f with WREG, skip if f < WREG DAW Syntax: [ label ] CPFSLT Syntax: [label] DAW Operands: 0 f 255 Operands: Operation: (f) –WREG), skip if (f) < (WREG) (unsigned comparison) 0 f 255 s [0,1] Operation: If [ [WREG<7:4> > 9].OR.[C = 1] ].AND. [WREG<3:0> > 9] then WREG<7:4> + 7 f<7:4>, s<7:4>; Status Affected: None Encoding: Description: f Decimal Adjust WREG Register 0011 0000 ffff ffff If [WREG<7:4> > 9].OR.
PIC17C7XX DECF Decrement f DECFSZ Decrement f, skip if 0 Syntax: [ label ] DECF f,d Syntax: [ label ] DECFSZ f,d Operands: 0 f 255 d [0,1] Operands: 0 f 255 d [0,1] Operation: (f) – 1 (dest) Operation: Status Affected: OV, C, DC, Z (f) – 1 (dest); skip if result = 0 Status Affected: None Encoding: 0000 Description: 011d ffff ffff Decrement register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f'.
PIC17C7XX DCFSNZ Decrement f, skip if not 0 GOTO Unconditional Branch Syntax: [label] DCFSNZ f,d Syntax: [ label ] Operands: 0 f 255 d [0,1] Operands: 0 k 8191 Operation: k PC<12:0>; k<12:8> PCLATH<4:0>, PC:13> PCLATH<7:5> Status Affected: None Operation: (f) – 1 (dest); skip if not 0 Status Affected: None Encoding: Description: 0010 011d ffff ffff The contents of register 'f' are decremented. If 'd' is 0, the result is placed in WREG.
PIC17C7XX INCF Increment f INCFSZ Increment f, skip if 0 Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] Operands: 0 f 255 d [0,1] Operation: (f) + 1 (dest) Operation: Status Affected: OV, C, DC, Z (f) + 1 (dest) skip if result = 0 Status Affected: None Encoding: 0001 Description: INCF f,d 010d ffff ffff The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f'.
PIC17C7XX INFSNZ Increment f, skip if not 0 IORLW Inclusive OR Literal with WREG Syntax: [label] Syntax: [ label ] Operands: 0 f 255 d [0,1] Operands: 0 k 255 Operation: Operation: (f) + 1 (dest), skip if not 0 (WREG) .OR. (k) (WREG) Status Affected: Z Status Affected: None Encoding: 0010 Description: INFSNZ f,d Encoding: 010d ffff ffff The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG.
PIC17C7XX IORWF Inclusive OR WREG with f LCALL Long Call Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] IORWF f,d Operation: (WREG) .OR. (f) (dest) Status Affected: Z Encoding: 0000 100d ffff ffff Description: Inclusive OR WREG with register 'f'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f'.
PIC17C7XX MOVFP Move f to p MOVLB Move Literal to low nibble in BSR Syntax: [label] Syntax: [ label ] Operands: 0 f 255 0 p 31 Operands: 0 k 15 Operation: k (BSR<3:0>) Status Affected: None MOVFP f,p Operation: (f) (p) Status Affected: None Encoding: Description: Encoding: 011p pppp ffff ffff Description: Move data from data memory location 'f' to data memory location 'p'.
PIC17C7XX Move Literal to high nibble in BSR MOVLW Syntax: [ label ] Syntax: [ label ] Operands: 0 k 15 Operands: 0 k 255 Operation: k (BSR<7:4>) Operation: k (WREG) Status Affected: None Status Affected: None MOVLR Encoding: Description: MOVLR k 1011 101x kkkk uuuu The 4-bit literal 'k' is loaded into the most significant 4-bits of the Bank Select Register (BSR). Only the high 4-bits of the Bank Select Register are affected. The lower half of the BSR is unchanged.
PIC17C7XX MOVPF Move p to f MOVWF Move WREG to f Syntax: [label] Syntax: [ label ] Operands: 0 f 255 0 p 31 Operands: 0 f 255 Operation: (WREG) (f) Status Affected: None MOVPF p,f Operation: (p) (f) Status Affected: Z Encoding: Encoding: 010p Description: pppp ffff ffff Move data from data memory location 'p' to data memory location 'f'. Location 'f' can be anywhere in the 256 byte data space (00h to FFh), while 'p' can be 00h to 1Fh.
PIC17C7XX MULLW Multiply Literal with WREG MULWF Multiply WREG with f Syntax: [ label ] Syntax: [ label ] Operands: 0 k 255 Operands: 0 f 255 Operation: (k x WREG) PRODH:PRODL Operation: (WREG x f) PRODH:PRODL Status Affected: None Status Affected: None Encoding: Description: 1011 MULLW 1100 k kkkk kkkk An unsigned multiplication is carried out between the contents of WREG and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair.
PIC17C7XX NEGW Negate W Syntax: [label] Operands: 0 f 255 s [0,1] Operands: None Operation: No operation Operation: WREG + 1 (f); WREG + 1 s Status Affected: None Status Affected: OV, C, DC, Z Encoding: 0010 Description: NEGW 110s f,s 1 Cycles: 1 ffff ffff Q Cycle Activity: Q1 Q2 Q3 Q4 Decode Read register 'f' Process Data Write register 'f' and other specified register Example: NEGW No Operation Syntax: [ label ] Encoding: WREG is negated using two’s compl
PIC17C7XX RETFIE Return from Interrupt RETLW Return Literal to WREG Syntax: [ label ] Syntax: [ label ] RETFIE RETLW k Operands: None Operands: 0 k 255 Operation: TOS (PC); 0 GLINTD; PCLATH is unchanged.
PIC17C7XX RETURN Return from Subroutine RLCF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] RLCF Operands: 0 f 255 d [0,1] Operation: f d; f<7> C; C d<0> Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter.
PIC17C7XX RLNCF Rotate Left f (no carry) RRCF Rotate Right f through Carry Syntax: [ label ] RLNCF Syntax: [ label ] Operands: 0 f 255 d [0,1] Operands: 0 f 255 d [0,1] Operation: f d; f<7> d<0> Operation: Status Affected: None f d; f<0> C; C d<7> Status Affected: C Encoding: 0010 Description: 001d f,d ffff ffff The contents of register 'f' are rotated one bit to the left. If 'd' is 0, the result is placed in WREG.
PIC17C7XX RRNCF Rotate Right f (no carry) SETF Set f Syntax: [ label ] Syntax: [ label ] Operands: 0 f 255 d [0,1] Operands: 0 f 255 s [0,1] Operation: f d; f<0> d<7> Operation: FFh f; FFh d Status Affected: None Status Affected: None Encoding: 0010 Description: RRNCF f,d 000d ffff ffff The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f'.
PIC17C7XX SLEEP Enter SLEEP mode Syntax: [ label ] SLEEP SUBLW Syntax: Operands: None Operands: 0 k 255 Operation: 00h WDT; 0 WDT postscaler; 1 TO; 0 PD Operation: k – (WREG) WREG) Status Affected: OV, C, DC, Z TO, PD Description: WREG is subtracted from the eight-bit literal 'k'. The result is placed in WREG. Words: 1 Cycles: 1 Status Affected: Encoding: 0000 Description: 0000 0000 Encoding: The processor is put into SLEEP mode with the oscillator stopped.
PIC17C7XX Subtract WREG from f with Borrow [ label ] SUBWFB f,d SUBWFB SUBWF Syntax: Subtract WREG from f [ label ] SUBWF f,d Operands: 0 f 255 d [0,1] Operands: 0 f 255 d [0,1] Operation: (f) – (W) dest) Operation: (f) – (W) – C dest) Status Affected: OV, C, DC, Z Status Affected: OV, C, DC, Z Encoding: 0000 Description: 010d ffff Syntax: ffff Subtract WREG from register 'f' (2’s complement method). If 'd' is 0, the result is stored in WREG.
PIC17C7XX SWAPF Swap f TABLRD Table Read Syntax: [ label ] SWAPF f,d Syntax: [ label ] TABLRD t,i,f Operands: 0 f 255 d [0,1] Operands: Operation: f<3:0> dest<7:4>; f<7:4> dest<3:0> 0 f 255 i [0,1] t [0,1] Operation: If t = 1, TBLATH f; If t = 0, TBLATL f; Prog Mem (TBLPTR) TBLAT; If i = 1, TBLPTR + 1 TBLPTR If i = 0, TBLPTR is unchanged Status Affected: None Status Affected: None Encoding: 0001 110d ffff ffff Description: The upper and lower nibbles of re
PIC17C7XX TABLRD Table Read TABLWT Table Write Example1: TABLRD Syntax: [ label ] TABLWT t,i,f Operands: 0 f 255 i [0,1] t [0,1] Operation: If t = 0, f TBLATL; If t = 1, f TBLATH; TBLAT Prog Mem (TBLPTR); If i = 1, TBLPTR + 1 TBLPTR If i = 0, TBLPTR is unchanged Status Affected: None 1, 1, REG ; Before Instruction REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR) = = = = = 0x53 0xAA 0x55 0xA356 0x1234 After Instruction (table write completion) REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR)
PIC17C7XX TABLWT Table Write TLRD Table Latch Read Example1: TABLWT Syntax: [ label ] TLRD t,f Operands: 0 f 255 t [0,1] Operation: If t = 0, TBLATL f; If t = 1, TBLATH f Status Affected: None 1, 1, REG Before Instruction REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR) = = = = = 0x53 0xAA 0x55 0xA356 0xFFFF After Instruction (table write completion) REG TBLATH TBLATL TBLPTR MEMORY(TBLPTR - 1) Example 2: TABLWT = = = = = 0x53 0x53 0x55 0xA357 0x5355 Encoding: 1010 Description: 0,
PIC17C7XX TLWT Table Latch Write TSTFSZ Test f, skip if 0 Syntax: [ label ] TLWT t,f Syntax: [ label ] TSTFSZ f Operands: 0 f 255 t [0,1] Operands: 0 f 255 Operation: skip if f = 0 If t = 0, f TBLATL; If t = 1, f TBLATH Status Affected: None Operation: Status Affected: Encoding: Encoding: 1010 01tx ffff If t = 1; high byte is written 1 Cycles: 1 (2) This instruction is used in conjunction with TABLWT to transfer data from data memory to program memory.
PIC17C7XX Exclusive OR Literal with WREG XORWF Syntax: [ label ] XORLW k Syntax: [ label ] XORWF Operands: 0 k 255 Operands: Operation: (WREG) .XOR. k WREG) 0 f 255 d [0,1] Status Affected: Z Operation: (WREG) .XOR. (f) dest) Status Affected: Z XORLW Encoding: 1011 Description: 0100 kkkk kkkk The contents of WREG are XOR’ed with the 8-bit literal 'k'. The result is placed in WREG.
PIC17C7XX NOTES: DS30289C-page 232 1998-2013 Microchip Technology Inc.
PIC17C7XX 19.
PIC17C7XX 19.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC17C7XX 19.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC16F87X and can be used to develop for this and other PIC microcontrollers from the PIC16CXXX family. The MPLAB ICD utilizes the in-circuit debugging capability built into the PIC16F87X.
PIC17C7XX 19.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X 1998-2013 Microchip Technology Inc. † † * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
PIC17C7XX NOTES: DS30289C-page 238 1998-2013 Microchip Technology Inc.
PIC17C7XX 20.0 PIC17C7XX ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias.............................................................................................................-55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ..............................................................................
PIC17C7XX FIGURE 20-1: PIC17C7XX-33 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC17C7XX-33 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 33 MHz Frequency FIGURE 20-2: PIC17C7XX-16 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC17C7XX-16 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 16 MHz Frequency DS30289C-page 240 1998-2013 Microchip Technology Inc.
PIC17C7XX FIGURE 20-3: PIC17LC7XX-08 VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V 4.5 V 4.0 V PIC17LC7XX-08 3.5 V 3.0 V 2.5 V 2.0 V 8 MHz Frequency FIGURE 20-4: PIC17C7XX/CL VOLTAGE-FREQUENCY GRAPH 6.0 V 5.5 V Voltage 5.0 V PIC17C7XX/CL 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 8 MHz 33 MHz Frequency 1998-2013 Microchip Technology Inc.
PIC17C7XX 20.1 DC Characteristics PIC17LC7XX-08 (Commercial, Industrial) PIC17C7XX-16 (Commercial, Industrial, Extended) PIC17C7XX-33 (Commercial, Industrial, Extended) Param. No.
PIC17C7XX PIC17LC7XX-08 (Commercial, Industrial) PIC17C7XX-16 (Commercial, Industrial, Extended) PIC17C7XX-33 (Commercial, Industrial, Extended) Param. No.
PIC17C7XX 20.2 DC Characteristics: PIC17C7XX-16 (Commercial, Industrial, Extended) PIC17C7XX-33 (Commercial, Industrial, Extended) PIC17LC7XX-08 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended -40°C TA +85°C for industrial 0°C TA +70°C for commercial Operating voltage VDD range as described in Section 20.1 DC CHARACTERISTICS Param. No.
PIC17C7XX Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended -40°C TA +85°C for industrial 0°C TA +70°C for commercial Operating voltage VDD range as described in Section 20.1 DC CHARACTERISTICS Param. No.
PIC17C7XX Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C for extended -40°C TA +85°C for industrial 0°C TA +70°C for commercial Operating voltage VDD range as described in Section 20.1 DC CHARACTERISTICS Param. No.
PIC17C7XX 20.3 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase symbols (pp) and their meanings: pp ad Address/Data al ALE cc Capture1 and Capture2 ck CLKOUT or clock dt Data in in INT pin io I/O port mc MCLR oe OE os OSC1 Uppercase symbols and their meanings: S D Driven E Edge F Fall H High I Invalid (Hi-impedance) 1998-2013 Microchip Technology Inc. 3. TCC:ST 4.
PIC17C7XX FIGURE 20-5: PARAMETER MEASUREMENT INFORMATION All timings are measured between high and low measurement points as indicated below. INPUT LEVEL CONDITIONS PORTC, D, E, F, G, H and J pins VIH = 2.4V VIL = 0.4V Data in valid All other input pins Data in invalid VIH = 0.9VDD VIL = 0.1VDD Data in valid Data in invalid OUTPUT LEVEL CONDITIONS 0.25V VOH = 0.7VDD VDD/2 VOL = 0.3VDD 0.25V 0.25V 0.25V Data out valid Output hi-impedance Data out invalid Output driven 0.9 VDD 0.
PIC17C7XX 20.4 Timing Diagrams and Specifications FIGURE 20-6: EXTERNAL CLOCK TIMING Q4 Q1 Q3 Q2 Q4 Q1 OSC1 3 1 3 2 4 4 OSC2 † † In EC and RC modes only. TABLE 20-1: Param No.
PIC17C7XX FIGURE 20-7: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 22 23 OSC2 † 12 13 18 14 16 19 I/O Pin (input) 15 17 I/O Pin (output) New Value Old Value 20, 21 † In EC and RC modes only. TABLE 20-2: Param No.
PIC17C7XX FIGURE 20-8: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET TIMING VDD MCLR 30 Internal POR/BOR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 35 Address/ Data TABLE 20-3: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS Param. No.
PIC17C7XX FIGURE 20-9: TIMER0 EXTERNAL CLOCK TIMINGS RA1/T0CKI 40 41 42 TABLE 20-4: Param No. TIMER0 EXTERNAL CLOCK REQUIREMENTS Sym 40 Characteristic Tt0H T0CKI High Pulse Width Min No Prescaler Tt0L T0CKI Low Pulse Width No Prescaler † Tt0P T0CKI Period Units — — ns 10 — — ns 0.5TCY + 20 — — ns 10 — — ns Greater of: 20 ns or TCY + 40 N — — ns With Prescaler 42 Max 0.5TCY + 20 With Prescaler 41 Typ† Conditions N = prescale value (1, 2, 4, ...
PIC17C7XX FIGURE 20-11: CAPTURE TIMINGS CAP pin (Capture mode) 50 51 52 TABLE 20-6: Param No. CAPTURE REQUIREMENTS Sym Characteristic 50 TccL 51 TccH Capture pin input high time 52 TccP Capture pin input period † Capture pin input low time Min Typ † Max Unit s Conditions 10 — — ns 10 — — ns 2TCY N — — ns Max Units N = prescale value (4 or 16) Data in “Typ” column is at 5V, 25C unless otherwise stated.
PIC17C7XX FIGURE 20-13: SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 BIT6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 20-5 for load conditions. TABLE 20-8: Param. No. SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Symbol Characteristic 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (Slave mode) 71A 72 Typ† Max Units Tcy — — ns Continuous 1.
PIC17C7XX FIGURE 20-14: SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 Note: TABLE 20-9: Param. No. 71 SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Symbol TscH 71A 72 Refer to Figure 20-5 for load conditions. Characteristic SCK input high time (Slave mode) Min Typ† Max Units ns Continuous 1.25TCY + 30 — — Single Byte 40 — — ns Continuous 1.
PIC17C7XX FIGURE 20-15: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb BIT6 - - - - - -1 77 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN 74 73 Note: Refer to Figure 20-5 for load conditions. TABLE 20-10: SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param. No.
PIC17C7XX FIGURE 20-16: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN Note: 77 BIT6 - - - -1 LSb IN 74 Refer to Figure 20-5 for load conditions. TABLE 20-11: SPI MODE REQUIREMENTS (SLAVE MODE, CKE = 1) Param. No. Symbol Characteristic 70 TssL2scH, TssL2scL SS to SCK or SCK input 71 TscH SCK input high time (Slave mode) 71A 72 Min Typ† Max Units Tcy — — ns ns Continuous 1.
PIC17C7XX FIGURE 20-17: I2C BUS START/STOP BITS TIMING SCL 93 91 90 92 SDA STOP Condition START Condition Note: Refer to Figure 20-5 for load conditions. TABLE 20-12: I2C BUS START/STOP BITS REQUIREMENTS Param. No.
PIC17C7XX FIGURE 20-18: I2C BUS DATA TIMING 103 102 100 101 SCL 90 106 91 92 107 SDA In 110 109 109 SDA Out Note: Refer to Figure 20-5 for load conditions. TABLE 20-13: I2C BUS DATA REQUIREMENTS Param No.
PIC17C7XX Param No. Sym 110 Tbuf D102 Cb Characteristic Bus free time Min Max Units 100 kHz mode 4.7 — ms 400 kHz mode 1.3 — ms 1 MHz mode(1) 0.5 — ms — 400 pF Bus capacitive loading Conditions Time the bus must be free before a new transmission can start Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode (400 KHz) I2C bus device can be used in a standard mode I2C bus system, but the parameter # 107 250 ns must then be met.
PIC17C7XX FIGURE 20-20: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING TX/CK pin 125 RX/DT pin 126 TABLE 20-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param No. † Sym Characteristic Min Typ† Max Unit s 125 TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK (DT setup time) 15 — — ns 126 TckL2dtl Data hold after CK (DT hold time) 15 — — ns Conditions Data in “Typ” column is at 5V, 25C unless otherwise stated. 1998-2013 Microchip Technology Inc.
PIC17C7XX FIGURE 20-21: USART ASYNCHRONOUS MODE START BIT DETECT START bit RX (RX/DT pin) 121A x16 CLK Q2, Q4 CLK 120A 123A TABLE 20-16: USART ASYNCHRONOUS MODE START BIT DETECT REQUIREMENTS Param No.
PIC17C7XX TABLE 20-18: A/D CONVERTER CHARACTERISTICS Param. No. Sym A01 NR A02 A03 A04 A05 A06 EABS EIL EDL EFS EOFF A10 — A20 VREF Characteristic Min Typ† Max Units — — 10 bit VREF+ = VDD = 5.12V, VSS VAIN VREF+ — — 10 bit (VREF+ — VREF-) 3.0V, VREF- VAIN VREF+ — — < 1 LSb VREF+ = VDD = 5.12V, VSS VAIN VREF+ — — < 1 LSb (VREF+ — VREF-) 3.0V, VREF- VAIN VREF+ — — < 1 LSb VREF+ = VDD = 5.
PIC17C7XX FIGURE 20-23: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 20-19: A/D CONVERSION REQUIREMENTS Param. No. Sym 130 TAD Characteristic A/D clock period Min Typ† Max PIC17CXXX 1.
PIC17C7XX FIGURE 20-24: MEMORY INTERFACE WRITE TIMING Q1 Q2 Q3 Q4 Q2 Q1 OSC1 ALE OE 151 WR 150 AD<15:0> 154 data out addr out addr out 152 153 TABLE 20-20: MEMORY INTERFACE WRITE REQUIREMENTS Param. No. Sym 150 TadV2alL 151 152 153 154 † TalL2adI TadV2wrL TwrH2adI TwrL Characteristic Min Typ† Max Unit s ns AD<15:0> (address) valid to PIC17CXXX 0.25TCY - 10 — — ALE (address setup time) PIC17LCXXX 0.
PIC17C7XX FIGURE 20-25: MEMORY INTERFACE READ TIMING Q1 Q2 Q3 Q4 Q1 Q2 OSC1 166 ALE 164 168 160 OE 165 Data in Addr out AD<15:0> Addr out 162 150 151 163 167 '1' WR 161 '1' TABLE 20-21: MEMORY INTERFACE READ REQUIREMENTS Param. No. 150 151 160 161 162 163 164 Sym TadV2alL TalL2adI Characteristic Unit s ns PIC17CXXX 0.25TCY - 10 — — PIC17LCXXX 0.
PIC17C7XX 21.0 PIC17C7XX DC AND AC CHARACTERISTICS The graphs and tables provided in this section are for design guidance and are not tested nor guaranteed. In some graphs or tables the data presented is outside specified operating range (e.g., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time.
PIC17C7XX FIGURE 21-2: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 4.0 3.5 R = 10k FOSC (MHz) 3.0 2.5 2.0 1.5 CEXT = 22 pF, T = +25C 1.0 0.5 R = 100k 0.0 4.0 4.5 5.0 5.5 6.0 6.5 6.0 6.5 VDD (Volts) FIGURE 21-3: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 4.0 3.5 R = 3.3k FOSC (MHz) 3.0 2.5 R = 5.1k 2.0 1.5 R = 10k 1.0 CEXT = 100 pF, T = +25C 0.5 R = 100k 0.0 4.0 4.5 5.0 5.5 VDD (Volts) DS30289C-page 268 1998-2013 Microchip Technology Inc.
PIC17C7XX FIGURE 21-4: TYPICAL RC OSCILLATOR FREQUENCY vs. VDD 2.0 1.8 1.6 1.4 R = 3.3k FOSC (MHz) 1.2 R = 5.1k 1.0 0.8 R = 10k 0.6 0.4 CEXT = 300 pF, T = +25C 0.2 R = 160k 0.0 4.0 4.5 5.0 5.5 6.0 6.5 VDD (Volts) TABLE 21-2: RC OSCILLATOR FREQUENCIES CEXT REXT 22 pF 10k 100k 3.3k 5.1k 10k 100k 3.3k 5.1k 10k 160k 100 pF 300 pF 1998-2013 Microchip Technology Inc. Average FOSC @ 5V, +25C 3.33 MHz 353 kHz 3.54 MHz 2.43 MHz 1.30 MHz 129 kHz 1.
PIC17C7XX FIGURE 21-5: TRANSCONDUCTANCE (gm) OF LF OSCILLATOR vs. VDD 500 450 400 350 Max @ -40C gm(A/V) 300 Typ @ +25C 250 200 150 Min @ +85C 100 50 0 2.5 3.0 3.5 4.0 4.5 5.5 5.0 6.0 VDD (Volts) FIGURE 21-6: TRANSCONDUCTANCE (gm) OF XT OSCILLATOR vs. VDD 20 18 Max @ -40C 16 14 Typ @ +25C gm(mA/V) 12 10 8 6 Min @ +85C 4 2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (Volts) DS30289C-page 270 1998-2013 Microchip Technology Inc.
PIC17C7XX FIGURE 21-7: TYPICAL IDD vs. FOSC OVER VDD (LF MODE) 1.2 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.0 5.5V 0.8 I DD (mA) 5.0V 4.5V 0.6 4.0V 3.5V 0.4 3.0V 0.2 0.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 F OSC (M Hz) MAXIMUM IDD vs. FOSC OVER VDD (LF MODE) FIGURE 21-8: 1.2 5.5V Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.0 5.0V 0.
PIC17C7XX FIGURE 21-9: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 16 5.5V Ty pic al: statistical s tatis tic al mean @ 25°C Typical: mean @ 25°C Max imum: mean + 3 (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 14 5.0V 12 4.5V IDD (mA) 10 8 6 4 4.0V 3.5V 2 3.0V 0 0 5 10 15 20 25 30 35 F OSC (M Hz ) FIGURE 21-10: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 18 5.
PIC17C7XX FIGURE 21-11: TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, ALL PERIPHERALS DISABLED, -40C to +125C) 6.0 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 5.0 M ax I PD (uA) 4.0 3.0 2.0 Typ 1.0 0.0 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V ) FIGURE 21-12: TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, BOR ENABLED, -40C to +125C) 2.0 1.
PIC17C7XX FIGURE 21-13: TYPICAL AND MAXIMUM IPD vs. VDD (SLEEP MODE, WDT ENABLED, -40C to +125C) 18 16 14 12 IPD (uA) M ax 10 Ty p 8 6 4 2 0 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V ) FIGURE 21-14: TYPICAL AND MAXIMUM IRBPU vs.
PIC17C7XX FIGURE 21-15: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs. VDD (-40C TO +125C) 40 Ty pic al: s tatis tic almean mean @ Typical: statistical @25°C 25°C Max imum: mean + 3 (-40°C to 125°C) Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3 (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 35 30 M ax (125C) WDT Period (ms) 25 20 15 Typ (25C) 10 M in (-40C) 5 0 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V ) FIGURE 21-16: TYPICAL WDT PERIOD vs.
PIC17C7XX FIGURE 21-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40C TO +125C) 5.0 4.5 Max 4.0 Ty p (25C) 3.5 VOH (V) 3.0 2.5 M in 2.0 1.5 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 1.0 0.5 0.0 0 5 10 15 20 25 I OH (-m A) FIGURE 21-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40C TO +125C) 1 .
PIC17C7XX FIGURE 21-19: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40C TO +125C) 3.0 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 2.5 V OH (V) 2.0 1.5 M in M ax 1.0 Ty p (25C) 0.5 0.0 0 5 10 15 20 25 I OH (-m A) FIGURE 21-20: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40C TO +125C) 2 .0 1 .
PIC17C7XX FIGURE 21-21: TYPICAL, MAXIMUM AND MINIMUM VIN vs. VDD (TTL INPUT, -40C to 125C) 1.8 1.6 Max 1.4 Ty p (25C) Min VIN (V) 1.2 1.0 0.8 0.6 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 0.4 0.2 0.0 3.0 3.5 4.0 4.5 5.0 5.5 V DD (V ) FIGURE 21-22: MAXIMUM AND MINIMUM VIN vs. VDD (ST Input, -40 C to +125C) 3 .
PIC17C7XX FIGURE 21-23: MAXIMUM AND MINIMUM VIN vs. VDD (I2C Input, -40C to +125C) 4 .0 Typical: statistical mean @ 25°C Maximum: mean + 3s (-40°C to 125°C) Minimum: mean – 3s (-40°C to 125°C) 3 .5 Ma x R is in g 3 .0 Min R is in g VIN (V) 2 .5 2 .0 Ma x Fa llin g Min Fa llin g 1 .5 1 .0 0 .5 0 .0 3 .0 3 .5 4 .0 4 .5 5 .0 5 .5 V DD (V ) 1998-2013 Microchip Technology Inc.
PIC17C7XX NOTES: DS30289C-page 280 1998-2013 Microchip Technology Inc.
PIC17C7XX 22.0 PACKAGING INFORMATION 22.1 Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC17C752 -08I/PT 0017CAE 68-Lead PLCC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 80-Lead TQFP e3 * Note: 0048CAE Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC17C7XX Package Marking Information (Cont.) 84-Lead PLCC XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN DS30289C-page 282 Example PIC17C766-08/L 0048CAE 1998-2013 Microchip Technology Inc.
PIC17C7XX 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC17C7XX 68-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D CH2 x 45 n12 CH1 x 45 A3 A2 32 A c B1 p B A1 D2 E2 Units Dimension Limits n p MIN INCHES* NOM 68 .050 17 .173 .153 .028 .029 .045 .005 .990 .990 .954 .954 .920 .920 .011 .029 .020 5 5 MAX MILLIMETERS NOM 68 1.27 17 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.
PIC17C7XX 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.
PIC17C7XX 84-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 #leads=n1 D1 D n 12 CH2 x 45 CH1 x 45 A3 A2 32 A c B1 p B A1 D2 E2 Units Dimension Limits n p INCHES* NOM 68 .050 17 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .985 .990 .985 .990 .950 .954 .950 .954 .890 .920 .890 .920 .008 .011 .026 .029 .013 .
PIC17C7XX APPENDIX A: MODIFICATIONS APPENDIX B: COMPATIBILITY The following is the list of modifications over the PIC16CXX microcontroller family: To convert code written for PIC16CXXX to PIC17CXXX, the user should take the following steps: 1. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. Instruction word length is increased to 16-bit.
PIC17C7XX APPENDIX C: WHAT’S NEW This is a new Data Sheet for the Following Devices: • • • • PIC17C752 PIC17C756A PIC17C762 PIC17C766 This Data Sheet is based on the PIC17C75X Data Sheet (DS30246A). APPENDIX D: WHAT’S CHANGED Clarified the TAD vs. device maximum operating frequency tables in Section 16.2. Added device characteristic graphs and charts in Section 21. Removed the “Preliminary” status from the entire document. Revision C (January 2013) Added a note to each package outline drawing.
PIC17C7XX INDEX A B A/D Bank Select Register (BSR) ............................................... 57 Banking......................................................................... 46, 57 Baud Rate Formula........................................................... 120 Baud Rate Generator ....................................................... 153 Baud Rate Generator (BRG) ............................................ 120 Baud Rates Asynchronous Mode.................................................
PIC17C7XX Bus Collision During a RESTART Condition..................... 173 Bus Collision During a START Condition.......................... 171 Bus Collision During a STOP Condition............................ 174 Bus Collision Interrupt Enable, BCLIE ................................ 36 Bus Collision Interrupt Flag bit, BCLIF ................................ 38 C C.................................................................................... 11, 51 CA1/PR3 ...........................................
PIC17C7XX F Family of Devices PIC17C75X ................................................................... 8 FERR ................................................................................ 125 Flowcharts Acknowledge............................................................. 166 Master Receiver........................................................ 163 Master Transmit ........................................................ 160 RESTART Condition .................................................
PIC17C7XX BTG........................................................................... 206 CALL ......................................................................... 207 CLRF......................................................................... 207 CLRWDT................................................................... 208 COMF ....................................................................... 208 CPFSEQ ................................................................... 209 CPFSGT .........
PIC17C7XX MOVPF ....................................................................... 46, 218 MOVWF ............................................................................ 218 MPLAB Integrated Development Environment Software .. 233 MULLW ............................................................................. 219 Multi-Master Communication ............................................ 170 Multi-Master Mode ............................................................
PIC17C7XX R R/W ................................................................................... 134 R/W bit .............................................................................. 145 R/W bit .............................................................................. 145 RA1/T0CKI pin .................................................................... 97 RBIE.................................................................................... 35 RBIF ...........................................
PIC17C7XX SEEVAL Evaluation and Programming System................ 236 Serial Clock, SCK ............................................................. 137 Serial Clock, SCL .............................................................. 144 Serial Data Address, SDA................................................. 144 Serial Data In, SDI ............................................................ 137 Serial Data Out, SDO........................................................ 137 SETF .......................
PIC17C7XX Timer0 ................................................................................. 97 Timer1 16-bit Mode ............................................................... 105 Clock Source Select.................................................. 101 On bit ................................................................ 102, 103 Section .............................................................. 101, 104 Timer2 16-bit Mode ...............................................................
PIC17C7XX TXREG2........................................................................ 27, 49 TXSTA .............................................................. 126, 130, 132 TXSTA Register TXEN Bit ......................................... 34, 51, 97, 101, 117 TXSTA1 ........................................................................ 27, 48 TXSTA2 ........................................................................ 27, 49 U UA ..................................................................
PIC17C7XX NOTES: DS30289C-page 298 1998-2013 Microchip Technology Inc.
PIC17C7XX ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.
PIC17C7XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet.
PIC17C7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device Device X Temperature Range /XX XXX Package Pattern Examples: a) PIC17C756 – 16L Commercial Temp., PLCC package, 16 MHz, normal VDD limits b) PIC17LC756–08/PT Commercial Temp., TQFP package, 8MHz, extended VDD limits c) PIC17C756–33I/PT Industrial Temp.
PIC17C7XX NOTES: DS30289C-page302 1998-2013 Microchip Technology Inc.
PIC17C7XX NOTES: 1998-2013 Microchip Technology Inc.
PIC17C7XX DS30289C-page 304 1998-2013 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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