Datasheet

PIC17C7XX
DS30289C-page 94  1998-2013 Microchip Technology Inc.
10.10.2 SUCCESSIVE OPERATIONS ON I/O
PORTS
The actual write to an I/O port happens at the end of an
instruction cycle, whereas for reading, the data must be
valid at the beginning of the instruction cycle
(Figure 10-20). Therefore, care must be exercised if a
write followed by a read operation is carried out on the
same I/O port. The sequence of instructions should be
such to allow the pin voltage to stabilize (load depen-
dent) before executing the instruction that reads the
values on that I/O port. Otherwise, the previous state of
that pin may be read into the CPU, rather than the
“new” state. When in doubt, it is better to separate
these instructions with a NOP, or another instruction
not accessing this I/O port.
Figure 10-21 shows the I/O model which causes this
situation. As the effective capacitance (C) becomes
larger, the rise/fall time of the I/O pin increases. As the
device frequency increases, or the effective capaci-
tance increases, the possibility of this subsequent
PORTx read-modify-write instruction issue increases.
This effective capacitance includes the effects of the
board traces.
The best way to address this is to add a series resistor
at the I/O pin. This resistor allows the I/O pin to get to
the desired level before the next instruction.
The use of NOP instructions between the subsequent
PORTx read-modify-write instructions, is a lower cost
solution, but has the issue that the number of NOP
instructions is dependent on the effective capacitance
C and the frequency of the device.
FIGURE 10-20: SUCCESSIVE I/O OPERATION
FIGURE 10-21: I/O CONNECTION ISSUES
PC PC + 1 PC + 2
PC + 3
Q1 Q2
Q3
Q4
Q1 Q2
Q3
Q4
Q1 Q2
Q3
Q4
Q1 Q2
Q3
Q4
Instruction
Fetched
RB7:RB0
MOVWF PORTB
write to
PORTB
NOP
Port pin
sampled here
NOP
MOVF PORTB,W
Instruction
Executed
MOVWF PORTB
write to
PORTB
NOPMOVF PORTB,W
Note:
This example shows a write to PORTB,
followed by a read from PORTB.
Note that:
data setup time = (0.25T
CY - TPD)
where T
CY = instruction cycle
T
PD = propagation delay
Therefore, at higher clock frequencies, a
write followed by a read may be problematic.
PIC17CXXX
I/O
C
(1)
Q4 Q1 Q2 Q3 Q4 Q1
VIL
BSF PORTx, PINy
Q2 Q3
BSF PORTx, PINz
PORTx, PINy
Read PORTx, PINy as low
BSF PORTx, PINz clears the value
to be driven on the PORTx, PINy pin.
Note 1: This is not a capacitor to ground, but the effective
capacitive loading on the trace.