Datasheet

PIC17C7XX
DS30289C-page 48  1998-2013 Microchip Technology Inc.
TABLE 7-3: SPECIAL FUNCTION REGISTERS
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR,
BOR
MCLR
,
WDT
Unbanked
00h INDF0 Uses contents of FSR0 to address Data Memory (not a physical register)
---- ---- ---- ----
01h FSR0 Indirect Data Memory Address Pointer 0
xxxx xxxx uuuu uuuu
02h PCL Low order 8-bits of PC 0000 0000 0000 0000
03h
(1)
PCLATH Holding Register for upper 8-bits of PC
0000 0000 uuuu uuuu
04h ALUSTA FS3 FS2 FS1 FS0 OV Z DC C 1111 xxxx 1111 uuuu
05h T0STA INTEDG T0SE T0CS T0PS3 T0PS2 T0PS1 T0PS0 —
0000 000- 0000 000-
06h
(2)
CPUSTA — — STKAV GLINTD TO PD POR BOR --11 11qq --11 qquu
07h INTSTA PEIF T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE
0000 0000 0000 0000
08h INDF1 Uses contents of FSR1 to address Data Memory (not a physical register)
---- ---- ---- ----
09h FSR1 Indirect Data Memory Address Pointer 1 xxxx xxxx uuuu uuuu
0Ah WREG Working Register
xxxx xxxx uuuu uuuu
0Bh TMR0L TMR0 Register; Low Byte
xxxx xxxx uuuu uuuu
0Ch TMR0H TMR0 Register; High Byte xxxx xxxx uuuu uuuu
0Dh TBLPTRL Low Byte of Program Memory Table Pointer
0000 0000 0000 0000
0Eh TBLPTRH High Byte of Program Memory Table Pointer
0000 0000 0000 0000
0Fh BSR Bank Select Register 0000 0000 0000 0000
Bank 0
10h PORTA
(4,6)
RBPU —
RA5/TX1/
CK1
RA4/RX1/
DT1
RA3/SDI/
SDA
RA2/SS
/
SCL
RA1/T0CKI RA0/INT
0-xx 11xx 0-uu 11uu
11h DDRB Data Direction Register for PORTB
1111 1111 1111 1111
12h PORTB
(4)
RB7/
SDO
RB6/
SCK
RB5/
TCLK3
RB4/
TCLK12
RB3/
PWM2
RB2/
PWM1
RB1/
CAP2
RB0/
CAP1
xxxx xxxx uuuu uuuu
13h RCSTA1 SPEN RX9 SREN CREN — FERR OERR RX9D
0000 -00x 0000 -00u
14h RCREG1 Serial Port Receive Register
xxxx xxxx uuuu uuuu
15h TXSTA1 CSRC TX9 TXEN SYNC — —TRMTTX9D
0000 --1x 0000 --1u
16h TXREG1 Serial Port Transmit Register (for USART1) xxxx xxxx uuuu uuuu
17h SPBRG1 Baud Rate Generator Register (for USART1)
0000 0000 0000 0000
Bank 1
10h DDRC
(5)
Data Direction Register for PORTC
1111 1111 1111 1111
11h PORTC
(4,5)
RC7/AD7 RC6/AD6 RC5/AD5 RC4/AD4 RC3/AD3 RC2/AD2 RC1/AD1 RC0/AD0 xxxx xxxx uuuu uuuu
12h DDRD
(5)
Data Direction Register for PORTD
1111 1111 1111 1111
13h PORTD
(4,5)
RD7/
AD15
RD6/
AD14
RD5/
AD13
RD4/
AD12
RD3/
AD11
RD2/
AD10
RD1/AD9 RD0/AD8
xxxx xxxx uuuu uuuu
14h DDRE
(5)
Data Direction Register for PORTE ---- 1111 ---- 1111
15h PORTE
(4,5)
— — — —
RE3/
CAP4
RE2/WR RE1/OE RE0/ALE
---- xxxx ---- uuuu
16h PIR1 RBIF TMR3IF TMR2IF TMR1IF CA2IF CA1IF TX1IF RC1IF
x000 0010 u000 0010
17h PIE1 RBIE TMR3IE TMR2IE TMR1IE CA2IE CA1IE TX1IE RC1IE
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends on condition.
Shaded cells are unimplemented, read as '0'.
Note 1: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<15:8> whose
contents are updated from, or transferred to, the upper byte of the program counter.
2: The TO
and PD status bits in CPUSTA are not affected by a MCLR Reset.
3: Bank 8 and associated registers are only implemented on the PIC17C76X devices.
4: This is the value that will be in the port output latch.
5: When the device is configured for Microprocessor or Extended Microcontroller mode, the operation of this port does not rely on these
registers.
6: On any device RESET, these pins are configured as inputs.