Datasheet

PIC17C7XX
DS30289C-page 266  1998-2013 Microchip Technology Inc.
FIGURE 20-25: MEMORY INTERFACE READ TIMING
TABLE 20-21: MEMORY INTERFACE READ REQUIREMENTS
OSC1
ALE
OE
AD<15:0>
WR
Q1 Q2 Q3
Data in
Addr out
150
151
160
166
165
162
163
161
'1'
'1'
Q4 Q1 Q2
Addr out
164
168
167
Param.
No.
Sym Characteristic Min Typ† Max
Unit
s
Conditions
150 TadV2alL AD15:AD0 (address) valid to PIC17CXXX 0.25T
CY - 10 — — ns
ALE (address setup time) PIC17LCXXX 0.25T
CY - 10 — —
151 TalL2adI ALE to address out invalid PIC17CXXX 5 — — ns
(address hold time) PIC17LCXXX 5 — —
160 TadZ2oeL AD15:AD0 hi-impedance to PIC17CXXX 0 — — ns
OE
 PIC17LCXXX 0 — —
161 ToeH2ad
D
OE
 to AD15:AD0 driven PIC17CXXX 0.25TCY - 15 — — ns
PIC17LCXXX 0.25T
CY - 15 — —
162 TadV2oeH Data in valid before OE
 PIC17CXXX 35 — — ns
(data setup time) PIC17LCXXX 45 — —
163 ToeH2adI OE
to data in invalid PIC17CXXX 0 — — ns
(data hold time) PIC17LCXXX 0 — —
164 TalH ALE pulse width PIC17CXXX — 0.25T
CY —ns
PIC17LCXXX — 0.25T
CY —
165 ToeL
OE
pulse width
PIC17CXXX 0.5T
CY - 35 — — ns
PIC17LCXXX 0.5T
CY - 35 — —
166 TalH2alH ALE to ALE(cycle time) PIC17CXXX — T
CY —ns
PIC17LCXXX — T
CY —
167 Tacc Address access time PIC17CXXX — — 0.75T
CY - 30 ns
PIC17LCXXX — — 0.75T
CY - 45
168 Toe Output enable access time PIC17CXXX — — 0.5T
CY - 45 ns
(OE
low to data valid) PIC17LCXXX — — 0.5TCY - 75
† Data in “Typ” column is at 5V, 25
°C unless otherwise stated.