Datasheet

PIC17C7XX
DS30289C-page 258  1998-2013 Microchip Technology Inc.
FIGURE 20-17: I
2
C BUS START/STOP BITS TIMING
TABLE 20-12: I
2
C BUS START/STOP BITS REQUIREMENTS
Note: Refer to Figure 20-5 for load conditions.
91
93
SCL
SDA
START
Condition
STOP
Condition
90
92
Param.
No.
Sym Characteristic Min
Ty
p
Max Units Conditions
90 Tsu:sta START condition 100 kHz mode 2(T
OSC)(BRG + 1) — — ns Only relevant for
Repeated Start condition
Setup time 400 kHz mode 2(T
OSC)(BRG + 1) — —
1 MHz mode
(1)
2(TOSC)(BRG + 1) — —
91 Thd:sta START condition 100 kHz mode 2(T
OSC)(BRG + 1) — — ns After this period, the first
clock pulse is generated
Hold time 400 kHz mode 2(T
OSC)(BRG + 1) — —
1 MHz mode
(1)
2(TOSC)(BRG + 1) — —
92 Tsu:sto STOP condition 100 kHz mode 2(T
OSC)(BRG + 1) — — ns
Setup time 400 kHz mode 2(T
OSC)(BRG + 1) — —
1 MHz mode
(1)
2(TOSC)(BRG + 1) — —
93 Thd:sto STOP condition 100 kHz mode 2(T
OSC)(BRG + 1) — — ns
Hold time 400 kHz mode 2(T
OSC)(BRG + 1) — —
1 MHz mode
(1)
2(TOSC)(BRG + 1) — —
Note 1: Maximum pin capacitance = 10 pF for all I
2
C pins.