Datasheet

PIC17C7XX
DS30289C-page 214  1998-2013 Microchip Technology Inc.
INFSNZ Increment f, skip if not 0
Syntax: [label] INFSNZ f,d
Operands: 0  f  255
d  [0,1]
Operation: (f) + 1  (dest),
skip if not 0
Status Affected: None
Encoding:
0010 010d ffff ffff
Description:
The contents of register 'f' are incre-
mented. If 'd' is 0, the result is placed in
WREG. If 'd' is 1, the result is placed
back in register 'f'.
If the result is not 0, the next instruction,
which is already fetched is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
Words: 1
Cycles: 1(2)
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
register 'f'
Process
Data
Write to
destination
If skip:
Q1 Q2 Q3 Q4
No
operation
No
operation
No
operation
No
operation
Example:
HERE INFSNZ REG, 1
ZERO
NZERO
Before Instruction
REG = REG
After Instruction
REG = REG + 1
If REG = 1;
PC = Address (ZERO)
If REG = 0;
PC = Address (NZERO)
IORLW Inclusive OR Literal with WREG
Syntax: [ label ] IORLW k
Operands: 0  k  255
Operation: (WREG) .OR. (k)  (WREG)
Status Affected: Z
Encoding:
1011 0011 kkkk kkkk
Description:
The contents of WREG are OR’ed with
the eight-bit literal 'k'. The result is
placed in WREG.
Words: 1
Cycles: 1
Q Cycle Activity:
Q1 Q2 Q3 Q4
Decode Read
literal 'k'
Process
Data
Write to
WREG
Example:
IORLW 0x35
Before Instruction
WREG = 0x9A
After Instruction
WREG = 0xBF