Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 193
PIC17C7XX
17.3 Watchdog Timer (WDT)
The Watchdog Timer’s function is to recover from soft-
ware malfunction, or to reset the device while in SLEEP
mode. The WDT uses an internal free running on-chip
RC oscillator for its clock source. This does not require
any external components. This RC oscillator is sepa-
rate from the RC oscillator of the OSC1/CLKIN pin.
That means that the WDT will run even if the clock on
the OSC1/CLKIN and OSC2/CLKOUT pins has been
stopped, for example, by execution of a SLEEP instruc-
tion. During normal operation, a WDT time-out gener-
ates a device RESET. The WDT can be permanently
disabled by programming the configuration bits
WDTPS1:WDTPS0 as '00' (Section 17.1).
Under normal operation, the WDT must be cleared on
a regular interval. This time must be less than the min-
imum WDT overflow time. Not clearing the WDT in this
time frame will cause the WDT to overflow and reset
the device.
17.3.1 WDT PERIOD
The WDT has a nominal time-out period of 12 ms (with
postscaler = 1). The time-out periods vary with temper-
ature, VDD and process variations from part to part (see
DC specs). If longer time-out periods are desired, con-
figuration bits should be used to enable the WDT with
a greater prescale. Thus, typical time-out periods up to
3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and its postscale setting and prevent it from timing out,
thus generating a device RESET condition.
The TO
bit in the CPUSTA register will be cleared upon
a WDT time-out.
17.3.2 CLEARING THE WDT AND
POSTSCALER
The WDT and postscaler are cleared when:
• The device is in the RESET state
•A SLEEP instruction is executed
•A CLRWDT instruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the RESET state.
17.3.3 WDT PROGRAMMING
CONSIDERATIONS
It should also be taken in account that under worst case
conditions (V
DD = Min., Temperature = Max., Max.
WDT postscaler), it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler become the Power-up Timer
whenever the PWRT is invoked.
17.3.4 WDT AS NORMAL TIMER
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 T
OSC cycles. On overflow, the TO bit
is cleared (device is not RESET). The CLRWDT instruc-
tion can be used to set the TO bit. This allows the WDT
to be a simple overflow timer. The simple timer does
not increment when in SLEEP.
FIGURE 17-1: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 17-2: REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
WDT
WDT Enable
Postscaler
4 - to - 1 MUX
WDTPS1:WDTPS0
On-chip RC
WDT Overflow
Oscillator
(1)
Note 1: This oscillator is separate from the external
RC oscillator on the OSC1 pin.
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
MCLR, WDT
—Config
See Figure 17-1 for location of WDTPSx bits in Configuration Word. (Note 1) (Note 1)
06h, Unbanked CPUSTA
— — STKAV GLINTD TO PD POR BOR
--11 11qq --11 qquu
Legend: - = unimplemented, read as '0', q = value depends on condition. Shaded cells are not used by the WDT.
Note 1: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.