Datasheet

PIC17C7XX
DS30289C-page 190  1998-2013 Microchip Technology Inc.
16.10 References
A good reference for understanding A/D converter is the
"Analog-Digital Conversion Handbook" third edition,
published by Prentice Hall (ISBN 0-13-03-2848-0).
TABLE 16-3: REGISTERS/BITS ASSOCIATED WITH A/D
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
POR,
BOR
MCLR, WDT
06h, unbanked CPUSTA
— — STAKAV GLINTD TO PD POR BOR --11 1100 --11 qq11
07h, unbanked INTSTA PEIF
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE
0000 0000 0000 0000
10h, Bank 4 PIR2
SSPIF BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF
000- 0010 000- 0010
11h, Bank 4 PIE2
SSPIE BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE
000- 0000 000- 0000
10h, Bank 5 DDRF Data Direction Register for PORTF 1111 1111 1111 1111
11h, Bank 5 PORTF
RF7/
AN11
RF6/
AN10
RF5/
AN9
RF4/
AN8
RF3/
AN7
RF2/
AN6
RF1/
AN5
RF0/
AN4
0000 0000 0000 0000
12h, Bank 5 DDRG Data Direction register for PORTG 1111 1111 1111 1111
13h, Bank 5 PORTG
RG7/
TX2/CK2
RG6/
RX2/DT2
RG5/
PWM3
RG4/
CAP3
RG3/
AN0/V
REF+
RG2/
AN1/VREF-
RG1/
AN2
RG0/
AN3
xxxx 0000 uuuu 0000
14h, Bank 5 ADCON0 CHS3 CHS2 CHS1 CHS0
— GO/DONE —ADON0000 -0-0 0000 -0-0
15h, Bank 5 ADCON1 ADCS1 ADCS0 ADFM
— PCFG3 PCFG2 PCFG1 PCFG0 000- 0000 000- 0000
16h, Bank 5 ADRESL A/D Result Low Register xxxx xxxx uuuu uuuu
17h, Bank 5 ADRESH A/D Result High Register xxxx xxxx uuuu uuuu
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion.
Note: Other (non power-up) RESETS include: external RESET through MCLR
and Watchdog Timer Reset.