Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 175
PIC17C7XX
15.3 Connection Considerations for
I
2
C Bus
For standard mode I
2
C bus devices, the values of
resistors R
p
R
s
in Figure 15-42 depends on the follow-
ing parameters:
• Supply voltage
• Bus capacitance
• Number of connected devices (input current +
leakage current)
The supply voltage limits the minimum value of resistor
R
p
due to the specified minimum sink current of 3 mA
at V
OL max = 0.4V for the specified output stages. For
example, with a supply voltage of V
DD = 5V +10% and
V
OL max = 0.4V at 3 mA, R
p
min = (5.5-0.4)/0.003 =
1.7 k V
DD as a function of R
p
is shown in Figure 15-
42. The desired noise margin of 0.1 V
DD for the low
level, limits the maximum value of R
s
. Series resistors
are optional and used to improve ESD susceptibility.
The bus capacitance is the total capacitance of wire,
connections and pins. This capacitance limits the max-
imum value of R
p
due to the specified rise time
(Figure 15-42).
The SMP bit is the slew rate control enabled bit. This bit
is in the SSPSTAT register and controls the slew rate of
the I/O pins when in I
2
C mode (master or slave).
FIGURE 15-42: SAMPLE DEVICE CONFIGURATION FOR I
2
C BUS
R
p
R
p
VDD + 10%
SDA
SCL
Note: I
2
C devices with input levels related to VDD must have one common supply line to which the pull-up resistor is
DEVICE
C
b
= 10 - 400 pF
R
s
R
s
also connected.