Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 169
PIC17C7XX
15.2.15 CLOCK ARBITRATION
Clock arbitration occurs when the master, during any
receive, transmit, or Repeated Start/Stop condition, de-
asserts the SCL pin (SCL allowed to float high). When
the SCL pin is allowed to float high, the baud rate gen-
erator (BRG) is suspended from counting until the SCL
pin is actually sampled high. When the SCL pin is sam-
pled high, the baud rate generator is reloaded with the
contents of SSPADD<6:0> and begins counting. This
ensures that the SCL high time will always be at least
one BRG rollover count, in the event that the clock is
held low by an external device (Figure 15-33).
15.2.16 SLEEP OPERATION
While in SLEEP mode, the I
2
C module can receive
addresses or data and when an address match or com-
plete byte transfer occurs, wake the processor from
SLEEP (if the SSP interrupt is enabled).
15.2.17 EFFECTS OF A RESET
A RESET disables the SSP module and terminates the
current transfer.
FIGURE 15-33: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE
SCL
SDA
BRG Overflow,
Release SCL,
If SCL = 1 Load BRG with
SSPADD<6:0>, and Start Count
BRG overflow occurs,
Release SCL, Slave device holds SCL low.
SCL = 1 BRG starts counting
clock high interval.
SCL line sampled once every machine cycle (T
OSC 4).
Hold off BRG until SCL is sampled high.
TBRG
TBRG
TBRG
to measure high time interval.