Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 165
PIC17C7XX
15.2.13 ACKNOWLEDGE SEQUENCE
TIMING
An acknowledge sequence is enabled by setting the
acknowledge sequence enable bit, ACKEN
(SSPCON2<4>). When this bit is set, the SCL pin is
pulled low and the contents of the acknowledge data bit
is presented on the SDA pin. If the user wishes to gen-
erate an acknowledge, then the ACKDT bit should be
cleared. If not, the user should set the ACKDT bit
before starting an acknowledge sequence. The baud
rate generator then counts for one rollover period
(T
BRG), and the SCL pin is de-asserted (pulled high).
When the SCL pin is sampled high (clock arbitration),
the baud rate generator counts for TBRG. The SCL pin
is then pulled low. Following this, the ACKEN bit is
automatically cleared, the baud rate generator is turned
off and the SSP module then goes into IDLE mode
(Figure 15-29).
15.2.13.1 WCOL Status Flag
If the user writes the SSPBUF when an acknowledge
sequence is in progress, then WCOL is set and the
contents of the buffer are unchanged (the write doesn’t
occur).
FIGURE 15-29: ACKNOWLEDGE SEQUENCE WAVEFORM
Note: TBRG = one baud rate generator period.
SDA
SCL
Set SSPIF at the End
Acknowledge Sequence Starts Here,
Write to SSPCON2
ACKEN Automatically Cleared
Cleared in
of Receive
ACK
8
ACKEN = 1, ACKDT = 0
D0
9
SSPIF
Software
Set SSPIF at the End
of Acknowledge Sequence
Cleared in
Software
TBRG
TBRG