Datasheet

PIC17C7XX
DS30289C-page 164  1998-2013 Microchip Technology Inc.
FIGURE 15-28: I
2
C MASTER MODE TIMING (RECEPTION 7-BIT ADDRESS)
P
9
87
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1
SDA SCL
12
3
4
5
6
7
8
9
12
3
4
5
678 9
1234
Bus Master Terminates
Transfer
ACK
Receiving Data from Slave
Receiving Data from Slave
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 1
Transmit Address to Slave
SSPIF BF
ACK
is Not Sent
Write to SSPCON2<0> (SEN = 1)
Write to SSPBUF Occurs Here
ACK
from Slave
Master Configured as a Receiver by Programming SSPCON2<3>, (RCEN = 1)
PEN bit = 1 Written Here
Data Shifted in on Falling Edge of CLK
Cleared in Software
Start XMIT
SEN = 0
SSPOV
SDA = 0, SCL = 1
while CPU
(SSPSTAT<0>)
ACK
Last bit is shifted into SSPSR and contents are unloaded into SSPBUF
Cleared in Software
Cleared in software
Set SSPIF interrupt at end of receive
Set P bit (SSPSTAT<4>) and SSPIF
Cleared in Software
ACK from Master
Set SSPIF at End
Set SSPIF Interrupt at End of Acknowledge Sequence
Set SSPIF Interrupt at End of Acknow- ledge sequence
of Receive
Set ACKEN, Start Acknowledge Sequence
SSPOV is Set Because SSPBUF is Still Full
SDA = ACKDT = 1
RCEN Cleared Automatically
RCEN = 1 Start Next Receive
Write to SSPCON2<4> to Start Acknowledge Sequence SDA = ACKDT (SSPCON2<5>) = 0
RCEN cleared automatically
Responds to SSPIF
ACKEN
Begin START Condition
Cleared in software
SDA = ACKDT = 0