Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 153
PIC17C7XX
A typical transmit sequence would go as follows:
a) The user generates a START Condition by set-
ting the START enable bit (SEN) in SSPCON2.
b) SSPIF is set. The module will wait the required
START time before any other operation takes
place.
c) The user loads the SSPBUF with address to
transmit.
d) Address is shifted out the SDA pin until all 8 bits
are transmitted.
e) The MSSP Module shifts in the ACK bit from the
slave device and writes its value into the
SSPCON2 register (SSPCON2<6>).
f) The module generates an interrupt at the end of
the ninth clock cycle by setting SSPIF.
g) The user loads the SSPBUF with eight bits of data.
h) DATA is shifted out the SDA pin until all 8 bits are
transmitted.
i) The MSSP Module shifts in the ACK bit from the
slave device, and writes its value into the
SSPCON2 register (SSPCON2<6>).
j) The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the SSPIF
bit.
k) The user generates a STOP condition by setting
the STOP enable bit PEN in SSPCON2.
l) Interrupt is generated once the STOP condition
is complete.
15.2.8 BAUD RATE GENERATOR
In I
2
C Master mode, the reload value for the BRG is
located in the lower 7 bits of the SSPADD register
(Figure 15-18). When the BRG is loaded with this
value, the BRG counts down to 0 and stops until
another reload has taken place. The BRG count is dec-
remented twice per instruction cycle (T
CY), on the Q2
and Q4 clock.
In I
2
C Master mode, the BRG is reloaded automatically.
If Clock Arbitration is taking place, for instance, the
BRG will be reloaded when the SCL pin is sampled
high (Figure 15-19).
FIGURE 15-18: BAUD RATE GENERATOR
BLOCK DIAGRAM
FIGURE 15-19: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION
SSPM3:SSPM0
BRG Down Counter
CLKOUT
F
OSC/4
SSPADD<6:0>
SSPM3:SSPM0
SCL
Reload
Control
Reload
SDA
SCL
SCL de-asserted but slave holds
DX-1DX
BRG
SCL is sampled high, reload takes
place and BRG starts its count.
03h 02h 01h 00h (hold off) 03h 02h
Reload
BRG
Value
SCL low (clock arbitration).
SCL allowed to transition high.
BRG decrements
(on Q2 and Q4 cycles).