Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 151
PIC17C7XX
15.2.5 MASTER MODE
Master mode of operation is supported by interrupt
generation on the detection of the START and STOP
conditions. The STOP (P) and START (S) bits are
cleared from a RESET, or when the MSSP module is
disabled. Control of the I
2
C bus may be taken when the
P bit is set, or the bus is idle, with both the S and P bits
clear.
In Master mode, the SCL and SDA lines are manipu-
lated by the MSSP hardware.
The following events will cause SSP Interrupt Flag bit,
SSPIF, to be set (SSP Interrupt if enabled):
• START condition
• STOP condition
• Data transfer byte transmitted/received
• Acknowledge transmit
• Repeated Start
FIGURE 15-17: SSP BLOCK DIAGRAM (I
2
C MASTER MODE)
Read Write
SSPSR
START bit, STOP bit,
SSPBUF
Internal
Data Bus
Set/Reset, S, P, WCOL (SSPSTAT)
Shift
Clock
MSb
LSb
SDA
Acknowledge
Generate
SCL
SCL In
Bus Collision
SDA In
Receive Enable
Clock Cntl
Clock Arbitrate/WCOL Detect
(hold off clock source)
SSPADD<6:0>
Baud
Set SSPIF, BCLIF
Reset ACKSTAT, PEN (SSPCON2)
Rate
Generator
SSPM3:SSPM0
START bit Detect,
STOP bit Detect
Write Collision Detect
Clock Arbitration
State Counter for
end of XMIT/RCV