Datasheet

PIC17C7XX
DS30289C-page 146  1998-2013 Microchip Technology Inc.
15.2.1.3 Slave Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W
bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and the SCL pin is held low.
The transmit data must be loaded into the SSPBUF
register, which also loads the SSPSR register. Then
SCL pin should be enabled by setting bit CKP
(SSPCON1<4>). The master must monitor the SCL pin
prior to asserting another clock pulse. The slave
devices may be holding off the master by stretching the
clock. The eight data bits are shifted out on the falling
edge of the SCL input. This ensures that the SDA sig-
nal is valid during the SCL high time (Figure 15-13).
An SSP interrupt is generated for each data transfer
byte. The SSPIF flag bit must be cleared in software,
and the SSPSTAT register is used to determine the sta-
tus of the byte transfer. The SSPIF flag bit is set on the
falling edge of the ninth clock pulse.
As a slave-transmitter, the ACK
pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the not ACK
is
latched by the slave, the slave logic is reset and the
slave then monitors for another occurrence of the
START bit. If the SDA line was low (ACK
), the transmit
data must be loaded into the SSPBUF register, which
also loads the SSPSR register. Then, the SCL pin
should be enabled by setting the CKP bit.
FIGURE 15-12: I
2
C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 15-13: I
2
C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
P
9
8
7
6
5
D0
D1
D2
D3D4
D5
D6D7
S
A7 A6 A5 A4
A3 A2 A1SDA
SCL
12
3
4
5
6
7
8
9
12
3
4
56
7
89
123
4
Bus Master
Terminates
Transfer
Bit SSPOV is set because the SSPBUF register is still full.
Cleared in software
SSPBUF register is read
ACK
Receiving Data
Receiving Data
D0
D1
D2
D3D4
D5
D6D7
ACK
R/W = 0
Receiving Address
SSPIF
BF (SSPSTAT<0>)
SSPOV (SSPCON1<6>)
ACK
ACK is not sent.
Not
SDA
SCL
SSPIF
BF (SSPSTAT<0>)
CKP (SSPCON1<4>)
A7 A6 A5 A4 A3 A2 A1
ACK
D7 D6 D5 D4 D3 D2 D1 D0
Not ACK
Transmitting Data
R/W
= 1
Receiving Address
123456789 123456789
P
Cleared in software
SSPBUF is written in software
From SSP Interrupt
Service Routine
Set bit after writing to SSPBUF
S
Data in
sampled
SCL held low
while CPU
responds to SSPIF
(the SSPBUF must be written to
before the CKP bit can be set)
R/W
= 0