Datasheet

PIC17C7XX
DS30289C-page 142  1998-2013 Microchip Technology Inc.
15.1.7 SLEEP OPERATION
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode and data to be
shifted into the SPI transmit/receive shift register.
When all 8-bits have been received, the MSSP inter-
rupt flag bit will be set and if enabled, will wake the
device from SLEEP.
15.1.8 EFFECTS OF A RESET
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-1: REGISTERS ASSOCIATED WITH SPI OPERATION
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, BOR MCLR, WDT
07h, Unbanked INTSTA PEIF
T0CKIF T0IF INTF PEIE T0CKIE T0IE INTE 0000 0000 0000 0000
10h, Bank 4 PIR2 SSPIF
BCLIF ADIF — CA4IF CA3IF TX2IF RC2IF
000- 0010 000- 0010
11h, Bank 4 PIE2 SSPIE
BCLIE ADIE — CA4IE CA3IE TX2IE RC2IE
000- 0000 000- 0000
14h, Bank 6 SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
11h, Bank 6 SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0
0000 0000 0000 0000
13h, Bank 6 SSPSTAT SMP CKE
D/A P S R/W UA BF 0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the SSP in SPI mode.