Datasheet

 1998-2013 Microchip Technology Inc. DS30289C-page 117
PIC17C7XX
14.0 UNIVERSAL SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (USART)
MODULES
Each USART module is a serial I/O module. There are
two USART modules that are available on the
PIC17C7XX. They are specified as USART1 and
USART2. The description of the operation of these mod-
ules is generic in regard to the register names and pin
names used. Table 14-1 shows the generic names that
are used in the description of operation and the actual
names for both USART1 and USART2. Since the control
bits in each register have the same function, their names
are the same (there is no need to differentiate).
The Transmit Status and Control Register (TXSTA) is
shown in Figure 14-1, while the Receive Status and
Control Register (RCSTA) is shown in Figure 14-2.
TABLE 14-1: USART MODULE GENERIC
NAMES
REGISTER 14-1: TXSTA1 REGISTER (ADDRESS: 15h, BANK 0)
TXSTA2 REGISTER (ADDRESS: 15h, BANK 4)
Generic Name USART1 Name USART2 Name
Registers
RCSTA RCSTA1 RCSTA2
TXSTA TXSTA1 TXSTA2
SPBRG SPBRG1 SPBRG2
RCREG RCREG1 RCREG2
TXREG TXREG1 TXREG2
Interrupt Control Bits
RCIE RC1IE RC2IE
RCIF RC1IF RC2IF
TXIE TX1IE TX2IE
TXIF TX1IF TX2IF
Pins
RX/DT RA4/RX1/DT1 RG6/RX2/DT2
TX/CK RA5/TX1/CK1 RG7/TX2/CK2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R-1 R/W-x
CSRC TX9 TXEN SYNC
— —TRMTTX9D
bit 7 bit 0
bit 7 CSRC: Clock Source Select bit
Synchronous mode:
1 = Master mode (clock generated internally from BRG)
0 = Slave mode (clock from external source)
Asynchronous mode
:
Don’t care
bit 6 TX9: 9-bit Transmit Select bit
1 = Selects 9-bit transmission
0 = Selects 8-bit transmission
bit 5 TXEN: Transmit Enable bit
1 = Transmit enabled
0 = Transmit disabled
SREN/CREN overrides TXEN in SYNC mode
bit 4 SYNC: USART Mode Select bit
(Synchronous/Asynchronous)
1 = Synchronous mode
0 = Asynchronous mode
bit 3-2 Unimplemented: Read as '0'
bit 1 TRMT: Transmit Shift Register (TSR) Empty bit
1 = TSR empty
0 = TSR full
bit 0 TX9D: 9th bit of Transmit Data (can be used to calculate the parity in software)
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR Reset ’1’ = Bit is set ’0’ = Bit is cleared x = Bit is unknown